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TCAN4550 Bus Off Recovery #628

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Jun 9, 2022
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26 changes: 19 additions & 7 deletions src/freertos_drivers/common/TCAN4550Can.cxx
Original file line number Diff line number Diff line change
Expand Up @@ -650,7 +650,7 @@ void *TCAN4550Can::entry()
spiStatus_ = register_read(STATUS);
status_ = register_read(INTERRUPT_STATUS);

MRAMMessage msg;
MRAMSPIMessage msg;
msg.cmd = READ;
msg.addrH = 0x10;
msg.addrL = 0x00;
Expand All @@ -659,7 +659,7 @@ void *TCAN4550Can::entry()
spi_ioc_transfer xfer[2];
xfer[0].tx_buf = (unsigned long)&msg;
xfer[0].rx_buf = 0;
xfer[0].len = sizeof(MRAMMessage);
xfer[0].len = sizeof(MRAMSPIMessage);
xfer[1].tx_buf = 0;
xfer[1].rx_buf = (unsigned long)regs_;
xfer[1].len = sizeof(regs_);
Expand Down Expand Up @@ -712,11 +712,6 @@ void *TCAN4550Can::entry()
// error passive state
++softErrorCount;
state_ = CAN_STATE_BUS_PASSIVE;

// cancel TX FIFO buffers
register_write(TXBCR, TX_FIFO_BUFFERS_MASK);

txBuf->signal_condition();
}
else
{
Expand All @@ -730,6 +725,23 @@ void *TCAN4550Can::entry()
// bus off
++busOffCount;
state_ = CAN_STATE_BUS_OFF;
// attempt recovery
Cccr cccr;
do
{
cccr.data = 0;
register_write(CCCR, cccr.data);
cccr.data = register_read(CCCR);
} while (cccr.init == 1);

// cancel TX FIFO buffers
register_write(TXBCR, TX_FIFO_BUFFERS_MASK);

txBuf->signal_condition();
}
else
{
state_ = CAN_STATE_ACTIVE;
}
}
}
Expand Down
4 changes: 4 additions & 0 deletions src/freertos_drivers/common/TCAN4550Can.hxx
Original file line number Diff line number Diff line change
Expand Up @@ -1124,6 +1124,10 @@ private:
MCANInterrupt mcanInterruptEnable_; ///< shadow for the interrupt enable
uint32_t txCompleteMask_; ///< shadow for the transmit complete buffer mask
uint8_t state_; ///< present bus state

// These bitmasks are protected from a read-modify-write race condition
// because they are only set from a thread context that holds the SPI bus
// mutex.
uint8_t txPending_ : 1; ///< waiting on a TX active event
uint8_t rxPending_ : 1; ///< waiting on a RX active event

Expand Down