Fix TivaSPI bug. The FIFO depth is just 8. (#572)

bakerstu · Sep 11, 2021 · 450b2eb · 450b2eb
1 parent 20548a5
commit 450b2eb
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/freertos_drivers/ti/TivaSPI.hxx b/src/freertos_drivers/ti/TivaSPI.hxx
@@ -189,7 +189,7 @@ private:
         do
         {
             /* fill TX FIFO but make sure we don't fill it to overflow */
-            if (tx_len && ((rx_len - tx_len) < (32 / sizeof(T))))
+            if (tx_len && ((rx_len - tx_len) < 8))
             {
                 if (data_put_non_blocking(*tx_buf) != 0)
                 {