Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Investigate slow div/rem #36

Open
mpardesh opened this issue Jan 17, 2023 · 0 comments
Open

Investigate slow div/rem #36

mpardesh opened this issue Jan 17, 2023 · 0 comments

Comments

@mpardesh
Copy link
Collaborator

udiv for 16 and 32 bits is too slow
@mpardesh mpardesh mentioned this issue Jan 17, 2023
Merged
@avanhatt avanhatt moved this from Todo to Nice to have in Implementation tasks Jan 30, 2023
@avanhatt avanhatt changed the title Investigate slow div Investigate slow div/rem Mar 21, 2023
@avanhatt avanhatt moved this from Nice to have to Todo in Implementation tasks Apr 13, 2023
avanhatt pushed a commit that referenced this issue May 26, 2023
@sunfishcode
Add a way to get a random u64. (#36)
e20ab42 
This anticipates WebAssembly/wasi-random#18.
avanhatt pushed a commit that referenced this issue May 26, 2023
@sunfishcode
Add a way to get a random u64. (#36)
fa34a13 
This anticipates WebAssembly/wasi-random#18.
avanhatt pushed a commit to wellesley-prog-sys/wasmtime that referenced this issue Oct 9, 2024
@mmcloughlin
isaspec: examples of immediate instruction semantics (bytecodeallianc…
129f504 
…e#113)

Extend the example semantics generator to generate examples of:

- `AluRRImm12`
- `AluRRImmLogic`
- `AluRRImmShift`
- `AluRRRShift`

Updates avanhatt#36
avanhatt pushed a commit to wellesley-prog-sys/wasmtime that referenced this issue Oct 9, 2024
@mmcloughlin
aslp: client support for opcode templates (bytecodealliance#116)
5ee5a8e 
Support opcode templates the the ASLp client.

This uses the format implemented in
mmcloughlin/aslp#4. The change is safe to land
now since in the common fixed 32-bit case, the formats are the same.

Updates avanhatt#36
avanhatt pushed a commit to wellesley-prog-sys/wasmtime that referenced this issue Oct 9, 2024
@mmcloughlin
aslp: bit manipulation helpers (bytecodealliance#117)
f056b6d 
Adds library functions for manipulating opcode templates.

Updates avanhatt#36
avanhatt pushed a commit to wellesley-prog-sys/wasmtime that referenced this issue Oct 9, 2024
@mmcloughlin
isaspec: generate AluRRImm12 spec (bytecodealliance#118)
7a4a0d1 
Generate `AluRRImm12` spec from ASLp.

This is the first requiring symbolic opcodes, so there are substantial
changes to support it:

* Updates ASLp dependency to fork containing experimental symbolic
opcode support
mmcloughlin/aslp@e5190a0
* Introduces `Bits` type to `isaspec` for manipulating opcode bitvectors
with symbolic fields.
* Generating ASLp semantics from an opcode template
* Validating an assembly template against the Cranelift assembler
* Updating verification model of `Imm12` to a struct type, and updating
related specs.

Updates avanhatt#36 avanhatt#35
avanhatt pushed a commit to wellesley-prog-sys/wasmtime that referenced this issue Oct 9, 2024
@mmcloughlin
isaspec: generate AluRRRShift spec (bytecodealliance#122)
0ba9782 
Generate `AluRRRShift` spec with ASLp.

This is the second example of a spec that relies on symbolic opcodes,
but it's slightly more challenging because the shift amount determines
the size of the symbolic field. Not only that, but the spec cases split
on `shiftop`, which is a struct type. In addition, the `lshl_from_imm64`
spec needed to be fixed.

Updates avanhatt#36 avanhatt#35
Closes bytecodealliance#120
avanhatt pushed a commit to wellesley-prog-sys/wasmtime that referenced this issue Oct 9, 2024
@mmcloughlin
isaspec: generate MovWide spec (bytecodealliance#127)
7659774 
Generate `MovWide` spec.

Updates avanhatt#36 avanhatt#35
avanhatt pushed a commit to wellesley-prog-sys/wasmtime that referenced this issue Oct 18, 2024
@mmcloughlin
isaspec: generate AluRRImm12 flags opcodes (bytecodealliance#155)
2d9be69 
Generates the flag-setting opcodes for `AluRRImm12`.

Relies on the CSE fix in ASLp added in
mmcloughlin/aslp#5.

Updates avanhatt#36 avanhatt#35
avanhatt pushed a commit to wellesley-prog-sys/wasmtime that referenced this issue Oct 23, 2024
@mmcloughlin
isaspec: generate memory operations with AMode.UnsignedOffset (byte…
c98e98e 
…codealliance#168)

Generate load/store specs using `AMode.UnsignedOffset`.

Updates avanhatt#36 avanhatt#49 avanhatt#35
avanhatt pushed a commit to wellesley-prog-sys/wasmtime that referenced this issue Oct 23, 2024
@mmcloughlin @avanhatt
isaspec: generate memory operations with AMode.UnsignedOffset (byte…
ec771c1 
…codealliance#168)

Generate load/store specs using `AMode.UnsignedOffset`.

Updates avanhatt#36 avanhatt#49 avanhatt#35
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
Implementation tasks
Status: Todo
Milestone
No milestone
Development

No branches or pull requests
1 participant
@mpardesh