Change VexRiscv configuration.

antmicro · Jul 15, 2019 · ab22e8f · ab22e8f
1 parent f799d28
commit ab22e8f
Showing 1 changed file with 13 additions and 0 deletions.
diff --git a/generate-renode-scripts.py b/generate-renode-scripts.py
@@ -161,10 +161,23 @@ def generate_cpu(time_provider):
         string: repl definition of the CPU
     """
     kind = constants['config_cpu_type']['value']
+    if 'config_cpu_variant' in constants:
+        variant = constants['config_cpu_variant']['value']
+    else:
+        variant = None
 
     if kind == 'VEXRISCV':
         result = """
 cpu: CPU.VexRiscv @ sysbus
+"""
+        if variant == 'LINUX':
+            result += """
+    cpuType: "rv32ima"
+    privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+"""
+        else:
+            result += """
+    cpuType: "rv32im"
 """
         if time_provider:
             result += """