disas: remove now useless cache

Now that we no longer do allocations on the emulation path, the cache is in fact counter productives, because it does allocations. Removing it gives us back another 25% of emulation time.
anisse · Jul 16, 2024 · de0a1c7 · de0a1c7
1 parent 93c5ccd
commit de0a1c7
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Showing 5 changed files with 4 additions and 74 deletions.
diff --git a/src/cpu.rs b/src/cpu.rs
@@ -1433,33 +1433,6 @@ pub fn run(s: &mut State, tstates_len: usize, debug: bool) -> Result<usize, Stri
     }
     Ok(tstates_ran)
 }
-pub use disas::DisasCache;
-pub fn run_cached(
-    c: &disas::DisasCache,
-    s: &mut State,
-    tstates_len: usize,
-    debug: bool,
-) -> Result<usize, String> {
-    let mut tstates_ran = 0;
-    let mut disas_target = [0_u8; 4];
-    while tstates_ran < tstates_len {
-        // TODO: split into m states, fetch etc
-        s.mem.fetch_range_safe(s.r.PC, &mut disas_target);
-        if let Some(op) = c.disas(&disas_target) {
-            if debug {
-                if s.halted {
-                    print!(".");
-                } else {
-                    print!("\n{:04X}: {:?} ", s.r.PC, op);
-                }
-            }
-            tstates_ran += run_op(s, &op)?;
-        } else {
-            return Err(format!("Unknown instruction(s)) {:02X?}", disas_target));
-        }
-    }
-    Ok(tstates_ran)
-}
 #[cfg(test)]
 mod tests {
     use crate::cpu::*;

diff --git a/src/disas.rs b/src/disas.rs
@@ -329,42 +329,6 @@ fn decode_operand_cond_cc(arg: u8) -> FlagCondition {
     }
 }
 
-const CACHE_SIZE: usize = 256;
-#[derive(Debug, PartialEq, Eq, Clone)]
-pub struct DisasCache {
-    cache: [Option<Rc<OpCode>>; CACHE_SIZE],
-}
-
-impl DisasCache {
-    pub fn init() -> DisasCache {
-        const INIT: Option<Rc<OpCode>> = None;
-        let mut dc = DisasCache {
-            cache: [INIT; CACHE_SIZE],
-        };
-
-        for (i, c) in dc.cache.iter_mut().enumerate() {
-            let opcode = disas(&[i as u8]);
-            if opcode.is_none() {
-                continue;
-            }
-            if let Some(op) = opcode {
-                if op.length == 1 {
-                    *c = Some(Rc::new(op));
-                }
-            }
-        }
-        //dbg!(&dc.cache);
-        dc
-    }
-    pub fn disas(&self, ins: &[u8]) -> Option<Rc<OpCode>> {
-        let i = ins[0] as usize; // | (ins[1] as usize) << 8;
-        if let Some(ref o) = self.cache[i] {
-            return Some(Rc::clone(o));
-        }
-        disas(ins).map(Rc::new)
-    }
-}
-
 #[inline]
 fn ins_to_data(ins: &[u8]) -> [u8; 4] {
     let mut data = [0; 4];

diff --git a/src/emu.rs b/src/emu.rs
@@ -51,7 +51,6 @@ pub use psg::AudioConf;
 pub use vdp::DisplayRefresh;
 
 pub struct Emulator {
-    cache: cpu::DisasCache,
     cpu: cpu::State,
     devs: Rc<devices::Devices>,
     render_area: vdp::RenderArea,
@@ -63,7 +62,6 @@ impl Emulator {
     pub fn init(rom: Vec<u8>, visible_only: bool, audio_conf: AudioConf) -> (Self, AudioCallback) {
         let (audio_tx, audio_rx) = psg::cmds();
         let mut emu = Self {
-            cache: cpu::DisasCache::init(),
             cpu: cpu::init(),
             devs: Rc::new(devices::Devices::new(audio_tx)),
             render_area: if visible_only {
@@ -88,8 +86,7 @@ impl Emulator {
             //println!("VDP sent an interrupt !");
             cpu::interrupt_mode_1(&mut self.cpu).unwrap();
         }
-        let cycles = cpu::run_cached(
-            &self.cache,
+        let cycles = cpu::run(
             &mut self.cpu,
             (CPU_CYCLES_PER_LINE as isize - self.over_cycles) as usize,
             false,

diff --git a/tests/z80test.rs b/tests/z80test.rs
@@ -25,8 +25,6 @@ fn z80doc() {
     z80common(include_bytes!("z80test/z80doc.tap"))
 }
 fn z80common(prog: &[u8]) {
-    let cache = gears::cpu::DisasCache::init();
-
     let mut state = cpu::init();
     state.mem = mem::Memory::init(mem::Mapper::ZX64K); // This test suite is for machines with more RAM
     state.io = io::RcDevice::new(ZxSpectrumIODevice {});
@@ -58,7 +56,7 @@ fn z80common(prog: &[u8]) {
     state.r.PC = load_addr;
     let mut msg = String::new();
     loop {
-        cpu::run_cached(&cache, &mut state, 1, false).unwrap();
+        cpu::run(&mut state, 1, false).unwrap();
         /*
         println!(
             "{:04X}: {:04X} | {:04X} {:04X} {:04X} {:04X} {:04X} {:04X} {:04X}",

diff --git a/tests/zexall.rs b/tests/zexall.rs
@@ -17,16 +17,14 @@ fn zexdoc() {
     zex(prog);
 }
 fn zex(prog: &[u8]) {
-    let cache = gears::cpu::DisasCache::init();
-
     let mut state = cpu::init();
     state.mem = mem::Memory::init(mem::Mapper::ZX64K); // This test suite is for machines with more RAM
     state.io = io::RcDevice::new(ZxSpectrumIODevice {});
 
     let load_addr = 0x100;
 
     for (addr, val) in prog.iter().enumerate() {
-        state.mem.set_u8(addr as u16 + load_addr as u16, *val);
+        state.mem.set_u8(addr as u16 + load_addr, *val);
     }
 
     // replace syscall 5
@@ -37,7 +35,7 @@ fn zex(prog: &[u8]) {
     state.r.PC = load_addr;
     let mut msg = String::new();
     loop {
-        cpu::run_cached(&cache, &mut state, 1, false).unwrap();
+        cpu::run(&mut state, 1, false).unwrap();
         /*
         println!(
             "{:04X}: {:04X} | {:04X} {:04X} {:04X} {:04X} {:04X} {:04X} {:04X}",