xtensa/esp32s3: Add XTWDT support

Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst

@@ -372,6 +372,22 @@ To test it, just run ``rand`` to get 32 randomly generated bytes::
     0000  98 b9 66 a2 a2 c0 a2 ae 09 70 93 d1 b5 91 86 c8  ..f......p......
     0010  8f 0e 0b 04 29 64 21 72 01 92 7c a2 27 60 6f 90  ....)d!r..|.'`o.
 
+rtc
+---
+
+This configuration demonstrates the use of the RTC driver through alarms.
+You can set an alarm, check its progress and receive a notification after it expires::
+
+    nsh> alarm 10
+    alarm_daemon started
+    alarm_daemon: Running
+    Opening /dev/rtc0
+    Alarm 0 set in 10 seconds
+    nsh> alarm -r
+    Opening /dev/rtc0
+    Alarm 0 is active with 10 seconds to expiration
+    nsh> alarm_daemon: alarm 0 received
+
 smp
 ---
 
@@ -534,3 +550,8 @@ To test it, just run the following::
   nsh> wdog -i /dev/watchdogx
 
 Where x is the watchdog instance.
+
+To test the XTWDT(/dev/watchdog3) an interrupt handler needs to be
+implemented because XTWDT does not have system reset feature. To implement
+an interrupt handler `WDIOC_CAPTURE` command can be used. When interrupt
+rises, XTAL32K clock can be restored with `WDIOC_RSTCLK` command.

arch/xtensa/src/esp32/esp32_rtc.c

@@ -1153,7 +1153,7 @@ void esp32_rtc_clk_set(void)
   enum esp32_rtc_fast_freq_e fast_freq = RTC_FAST_FREQ_8M;
   enum esp32_slow_clk_sel_e slow_clk = SLOW_CLK_150K;
 
-#if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS)
+#if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_XTAL)
   slow_clk = SLOW_CLK_32K_XTAL;
 #elif defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC)
   slow_clk = SLOW_CLK_32K_EXT_OSC;

arch/xtensa/src/esp32s3/Kconfig

@@ -703,6 +703,28 @@ config ESP32S3_RWDT
 		to have the RTC module reset, please, use the Timers' Module WDTs.
 		They will only reset Main System.
 
+config ESP32S3_XTWDT
+	bool "XTAL32K Watchdog Timer"
+	depends on ESP32S3_RTC_CLK_EXT_OSC || ESP32S3_RTC_CLK_EXT_XTAL
+	default n
+	select ESP32S3_WDT
+	select ESP32S3_RTCIO_IRQ
+	---help---
+		Includes XTWDT. This watchdog timer monitors the status of the
+		external 32 kHz crystal oscillator (XTAL32K). When XTAL32K_CLK works
+		as the clock source of RTC_SLOW_CLK and it stops oscillating, the
+		XTAL32K watchdog timer first switches to BACKUP32K_CLK derived from
+		RC_SLOW_CLK (if ESP32S3_XTWDT_BACKUP_CLK_ENABLE) and, then, generates
+		an interrupt that could be captured by WDIOC_CAPTURE.
+
+config ESP32S3_XTWDT_BACKUP_CLK_ENABLE
+	bool "Automatically switch to BACKUP32K_CLK when timer expires"
+	depends on ESP32S3_XTWDT
+	default y
+	help
+		Enable this to automatically switch to BACKUP32K_CLK as the source of
+		RTC_SLOW_CLK when the watchdog timer expires.
+
 config ESP32S3_RT_TIMER
 	bool "Real-Time Timer"
 	default n
@@ -1523,6 +1545,50 @@ config ESP32S3_FREERUN
 
 endmenu # Timer/Counter Configuration
 
+menu "RTC Configuration"
+	depends on ESP32S3_RTC
+
+choice ESP32S3_RTC_CLK_SRC
+	prompt "RTC clock source"
+	default ESP32S3_RTC_CLK_INT_RC
+	---help---
+		Choose which clock is used as RTC clock source.
+
+		- "Internal 150kHz oscillator" option provides lowest deep sleep current
+			consumption, and does not require extra external components. However
+			frequency stability with respect to temperature is poor, so time may
+			drift in deep/light sleep modes.
+		- "External 32kHz crystal" provides better frequency stability, at the
+			expense of slightly higher (1uA) deep sleep current consumption.
+		- "External 32kHz oscillator" allows using 32kHz clock generated by an
+			external circuit. In this case, external clock signal must be connected
+			to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal,
+			and <1V in case of square wave signal. Common mode voltage should be
+			0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude.
+			Additionally, 1nF capacitor must be connected between 32K_XP pin and
+			ground. 32K_XP pin can not be used as a GPIO in this case.
+		- "Internal 8.5MHz oscillator divided by 256" option results in higher
+			deep sleep current (by 5uA) but has better frequency stability than
+			the internal 150kHz oscillator. It does not require external components.
+
+config ESP32S3_RTC_CLK_INT_RC
+	bool "Internal 150kHz RC oscillator"
+
+config ESP32S3_RTC_CLK_EXT_XTAL
+	bool "External 32kHz crystal"
+	select ESP_SYSTEM_RTC_EXT_XTAL
+
+config ESP32S3_RTC_CLK_EXT_OSC
+	bool "External 32kHz oscillator at 32K_XN pin"
+	select ESP_SYSTEM_RTC_EXT_XTAL
+
+config ESP32S3_RTC_CLK_INT_8MD256
+	bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)"
+
+endchoice
+endmenu # "RTC Configuration"
+
+
 menu "Real-Time Timer Configuration"
 	depends on ESP32S3_RT_TIMER
 

arch/xtensa/src/esp32s3/esp32s3_rtc.c

@@ -1465,11 +1465,11 @@ void esp32s3_rtc_clk_set(void)
   enum esp32s3_rtc_fast_freq_e fast_freq = RTC_FAST_FREQ_8M;
   enum esp32s3_slow_clk_sel_e slow_clk = SLOW_CLK_150K;
 
-#if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS)
+#if defined(CONFIG_ESP32S3_RTC_CLK_EXT_XTAL)
   slow_clk = SLOW_CLK_32K_XTAL;
-#elif defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC)
+#elif defined(CONFIG_ESP32S3_RTC_CLK_EXT_OSC)
   slow_clk = SLOW_CLK_32K_EXT_OSC;
-#elif defined(CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256)
+#elif defined(CONFIG_ESP32S3_RTC_CLK_INT_8MD256)
   slow_clk = SLOW_CLK_8MD256;
 #endif
 

arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h

@@ -34,7 +34,7 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Name: esp32_rtc_driverinit
+ * Name: esp32s3_rtc_driverinit
  *
  * Description:
  *   Bind the configuration timer to a timer lower half instance and register
@@ -49,7 +49,7 @@
  *
  ****************************************************************************/
 
-int esp32_rtc_driverinit(void);
+int esp32s3_rtc_driverinit(void);
 
 #endif /* CONFIG_RTC_DRIVER */