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adrv9009: Updated interconnects #106

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adrv9009: Updated interconnects #106

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0d1c3fb
cpu_interconnect: Cascaded interconnect support
IstvanZsSzekely Sep 9, 2024
a8d84ff
adrv9009: Minor fixes
IstvanZsSzekely Oct 18, 2024
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8 changes: 4 additions & 4 deletions library/utilities/test_harness_system_bd.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -167,18 +167,18 @@ ad_cpu_interconnect 0x41200000 axi_intc
ad_mem_hp0_interconnect sys_mem_clk ddr_axi_vip/S_AXI

# connect mng_vip to ddr_vip
set_property -dict [list CONFIG.NUM_MI {2}] [get_bd_cells axi_axi_interconnect]
ad_connect axi_axi_interconnect/M01_AXI /axi_mem_interconnect/S00_AXI
set_property -dict [list CONFIG.NUM_MI {2}] [get_bd_cells axi_axi_interconnect_0]
ad_connect axi_axi_interconnect_0/M01_AXI /axi_mem_interconnect/S00_AXI

global sys_mem_clk_index
if { $use_smartconnect == 1} {
incr sys_mem_clk_index
set_property CONFIG.NUM_CLKS [expr $sys_mem_clk_index +1] [get_bd_cells axi_mem_interconnect]
ad_connect sys_cpu_clk axi_mem_interconnect/ACLK$sys_mem_clk_index
} else {
ad_connect sys_cpu_clk axi_axi_interconnect/M01_ACLK
ad_connect sys_cpu_clk axi_axi_interconnect_0/M01_ACLK
ad_connect sys_cpu_clk axi_mem_interconnect/S00_ACLK
ad_connect sys_cpu_resetn axi_axi_interconnect/M01_ARESETN
ad_connect sys_cpu_resetn axi_axi_interconnect_0/M01_ARESETN
ad_connect sys_cpu_resetn axi_mem_interconnect/S00_ARESETN
}

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4 changes: 4 additions & 0 deletions scripts/adi_sim.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,11 @@ proc adi_sim_project_xilinx {project_name {part "xc7vx485tffg1157-1"}} {
create_bd_design $design_name

global sys_zynq
global sys_cpu_interconnect_cascade

set sys_zynq -1
set sys_cpu_interconnect_cascade 1

if { ![info exists ad_project_params(CUSTOM_HARNESS)] || !$ad_project_params(CUSTOM_HARNESS) } {
source ../../../library/utilities/test_harness_system_bd.tcl
}
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18 changes: 6 additions & 12 deletions testbenches/project/adrv9009/system_bd.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -238,10 +238,8 @@ ad_connect rx_device_clk i_rx_jesd_exerciser/device_clk
ad_connect rx_device_clk i_rx_jesd_exerciser/link_clk
ad_connect ref_clk_ex i_rx_jesd_exerciser/ref_clk

set_property -dict [list CONFIG.NUM_MI {18}] [get_bd_cells axi_axi_interconnect]
ad_connect i_rx_jesd_exerciser/S00_AXI_0 axi_axi_interconnect/M17_AXI
ad_connect sys_cpu_clk axi_axi_interconnect/M17_ACLK
ad_connect sys_cpu_resetn axi_axi_interconnect/M17_ARESETN
set_property -dict [list CONFIG.NUM_MI {3}] [get_bd_cells axi_axi_interconnect_1]
ad_connect i_rx_jesd_exerciser/S00_AXI_0 axi_axi_interconnect_1/M02_AXI

create_bd_port -dir O ex_rx_sync
ad_connect ex_rx_sync i_rx_jesd_exerciser/rx_sync_0
Expand All @@ -260,10 +258,8 @@ ad_connect tx_device_clk i_tx_jesd_exerciser/device_clk
ad_connect tx_link_clk i_tx_jesd_exerciser/link_clk
ad_connect ref_clk_ex i_tx_jesd_exerciser/ref_clk

set_property -dict [list CONFIG.NUM_MI {19}] [get_bd_cells axi_axi_interconnect]
ad_connect i_tx_jesd_exerciser/S00_AXI_0 axi_axi_interconnect/M18_AXI
ad_connect sys_cpu_clk axi_axi_interconnect/M18_ACLK
ad_connect sys_cpu_resetn axi_axi_interconnect/M18_ARESETN
set_property -dict [list CONFIG.NUM_MI {4}] [get_bd_cells axi_axi_interconnect_1]
ad_connect i_tx_jesd_exerciser/S00_AXI_0 axi_axi_interconnect_1/M03_AXI

create_bd_port -dir I ex_tx_sync
ad_connect ex_tx_sync i_tx_jesd_exerciser/tx_sync_0
Expand Down Expand Up @@ -291,10 +287,8 @@ ad_connect tx_os_device_clk i_tx_os_jesd_exerciser/device_clk
ad_connect tx_os_device_clk i_tx_os_jesd_exerciser/link_clk
ad_connect ref_clk_ex i_tx_os_jesd_exerciser/ref_clk

set_property -dict [list CONFIG.NUM_MI {20}] [get_bd_cells axi_axi_interconnect]
ad_connect i_tx_os_jesd_exerciser/S00_AXI_0 axi_axi_interconnect/M19_AXI
ad_connect sys_cpu_clk axi_axi_interconnect/M19_ACLK
ad_connect sys_cpu_resetn axi_axi_interconnect/M19_ARESETN
set_property -dict [list CONFIG.NUM_MI {5}] [get_bd_cells axi_axi_interconnect_1]
ad_connect i_tx_os_jesd_exerciser/S00_AXI_0 axi_axi_interconnect_1/M04_AXI

create_bd_port -dir I ex_tx_os_sync
ad_connect ex_tx_os_sync i_tx_os_jesd_exerciser/tx_sync_0
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3 changes: 0 additions & 3 deletions testbenches/project/adrv9009/system_project.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -15,9 +15,6 @@ source "cfgs/${cfg_file}"
# Set the project name
set project_name [file rootname $cfg_file]

# Set to use SmartConnect or AXI Interconnect
set use_smartconnect 0

# Create the project
#adi_sim_project_xilinx $project_name "xcvm1802-vfvc1760-3HP-e-S"
adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e"
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