RISC-V: Allow both Zmmul and M

We got to talking about how Zmmul and M interact with each other riscv/riscv-isa-manual#869 , and it turns out that QEMU's behavior is slightly wrong: having Zmmul and M is a legal combination, it just means that the multiplication instructions are supported even when M is disabled at runtime via misa. This just stops overriding M from Zmmul, with that the other checks for the multiplication instructions work as per the ISA. Signed-off-by: Palmer Dabbelt <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
alistair23 · Jul 27, 2022 · 44602af · 44602af
1 parent 7b17a1a
commit 44602af
Showing 1 changed file with 0 additions and 5 deletions.
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
@@ -619,11 +619,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             cpu->cfg.ext_ifencei = true;
         }
 
-        if (cpu->cfg.ext_m && cpu->cfg.ext_zmmul) {
-            warn_report("Zmmul will override M");
-            cpu->cfg.ext_m = false;
-        }
-
         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
             error_setg(errp,
                        "I and E extensions are incompatible");