[bot] AutoMerging: merge all upstream's changes:

* https://github.com/coolsnowwolf/lede:
  kernel: bump 5.18 to 5.18.16 (coolsnowwolf#9892)
  kernel: bump 5.15 to 5.15.59 (coolsnowwolf#9891)
  kernel: refresh 5.19 patch (coolsnowwolf#9890)
  rockchip: 5.19: disable ntfs option (coolsnowwolf#9889)
  rockchip: refresh 5.19 patch
  rockchip: add kernel 5.19 support
  kernel: bump 5.10 to 5.10.135 (coolsnowwolf#9887)
  ntfs3-mount : add support kernel 5.19
  kernel: refresh RTL 5.19 patch

include/kernel-5.10

@@ -1,2 +1,2 @@
-LINUX_VERSION-5.10 = .134
-LINUX_KERNEL_HASH-5.10.134 = ec3513acdf033dd8f8ac2545cd1bb826b0669e151185e5f70408a5c9fe273269
+LINUX_VERSION-5.10 = .135
+LINUX_KERNEL_HASH-5.10.135 = e499a61be9ce670716dd27b5124bb9ef6c6bc0e8fab443abf717a77136543344

include/kernel-5.15

@@ -1,2 +1,2 @@
-LINUX_VERSION-5.15 = .58
-LINUX_KERNEL_HASH-5.15.58 = d75bd9579c4b318e6162e21c591878fd37efda0f79c5cdd0dc4eb9ea9dfc4fa8
+LINUX_VERSION-5.15 = .59
+LINUX_KERNEL_HASH-5.15.59 = e6ddc642057340db06b3b921c2b31bfed2c611359e8f144c3e5cf9c3ac33bccb

include/kernel-5.18

@@ -1,2 +1,2 @@
-LINUX_VERSION-5.18 = .15
-LINUX_KERNEL_HASH-5.18.15 = 69804febdc388a69dfb64493b7b58d402853de3a14144ea8db7fd67c30dcbe3c
+LINUX_VERSION-5.18 = .16
+LINUX_KERNEL_HASH-5.18.16 = f1f586251e63de14c86e5f95b96beb15a0434f1e6e21df788d123564af0d11ce

package/lean/ntfs3-mount/Makefile

@@ -10,7 +10,7 @@ define Package/ntfs3-mount
   CATEGORY:=Utilities
   SUBMENU:=Filesystem
   TITLE:=NTFS mount script for Paragon NTFS3 driver
-  DEPENDS:=+LINUX_5_4:kmod-fs-ntfs3-oot +(LINUX_5_15||LINUX_5_18):kmod-fs-ntfs3
+  DEPENDS:=+LINUX_5_4:kmod-fs-ntfs3-oot +(LINUX_5_15||LINUX_5_18||LINUX_5_19):kmod-fs-ntfs3
   PKGARCH:=all
 endef
 

package/lean/r8125/patches/020-5.19-support.patch

@@ -4,7 +4,7 @@
  #define FIRMWARE_8168FP_3   "rtl_nic/rtl8168fp-3.fw"
  #define FIRMWARE_8168FP_4   "rtl_nic/rtl8168fp-4.fw"
 
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0)
 +static inline void netif_set_gso_max_size(struct net_device *dev,
 +					  unsigned int size)
 +{

package/lean/r8152/patches/010-5.19-support.patch

@@ -4,7 +4,7 @@
  #define RTL_ADVERTISED_1000_FULL		BIT(5)
  #define RTL_ADVERTISED_2500_FULL		BIT(6)
 
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0)
 +static inline void netif_set_gso_max_size(struct net_device *dev,
 +					  unsigned int size)
 +{

package/lean/r8168/patches/030-5.19-support.patch

@@ -4,7 +4,7 @@
  #define FIRMWARE_8168FP_3   "rtl_nic/rtl8168fp-3.fw"
  #define FIRMWARE_8168FP_4   "rtl_nic/rtl8168fp-4.fw"
 
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0)
 +static inline void netif_set_gso_max_size(struct net_device *dev,
 +					  unsigned int size)
 +{

target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch

@@ -305,7 +305,7 @@
  	list_for_each_entry(p, head, list) {
 --- a/net/ipv4/tcp_output.c
 +++ b/net/ipv4/tcp_output.c
-@@ -612,48 +612,53 @@ static void tcp_options_write(__be32 *pt
+@@ -609,48 +609,53 @@ static void tcp_options_write(__be32 *pt
  	u16 options = opts->options;	/* mungable copy */
 
  	if (unlikely(OPTION_MD5 & options)) {
@@ -382,7 +382,7 @@
  	}
 
  	if (unlikely(opts->num_sack_blocks)) {
-@@ -661,16 +666,17 @@ static void tcp_options_write(__be32 *pt
+@@ -658,16 +663,17 @@ static void tcp_options_write(__be32 *pt
  			tp->duplicate_sack : tp->selective_acks;
  		int this_sack;
 
@@ -406,7 +406,7 @@
  		}
 
  		tp->rx_opt.dsack = 0;
-@@ -683,13 +689,14 @@ static void tcp_options_write(__be32 *pt
+@@ -680,13 +686,14 @@ static void tcp_options_write(__be32 *pt
 
  		if (foc->exp) {
  			len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len;
@@ -706,7 +706,7 @@
  EXPORT_SYMBOL(xfrm_parse_spi);
 --- a/net/ipv4/tcp_input.c
 +++ b/net/ipv4/tcp_input.c
-@@ -4092,14 +4092,16 @@ static bool tcp_parse_aligned_timestamp(
+@@ -4093,14 +4093,16 @@ static bool tcp_parse_aligned_timestamp(
  {
  	const __be32 *ptr = (const __be32 *)(th + 1);
 

target/linux/ath79/patches-5.15/910-unaligned_access_hacks.patch

@@ -305,7 +305,7 @@
  	list_for_each_entry(p, head, list) {
 --- a/net/ipv4/tcp_output.c
 +++ b/net/ipv4/tcp_output.c
-@@ -613,48 +613,53 @@ static void tcp_options_write(__be32 *pt
+@@ -610,48 +610,53 @@ static void tcp_options_write(__be32 *pt
  	u16 options = opts->options;	/* mungable copy */
 
  	if (unlikely(OPTION_MD5 & options)) {
@@ -382,7 +382,7 @@
  	}
 
  	if (unlikely(opts->num_sack_blocks)) {
-@@ -662,16 +667,17 @@ static void tcp_options_write(__be32 *pt
+@@ -659,16 +664,17 @@ static void tcp_options_write(__be32 *pt
  			tp->duplicate_sack : tp->selective_acks;
  		int this_sack;
 
@@ -406,7 +406,7 @@
  		}
 
  		tp->rx_opt.dsack = 0;
-@@ -684,13 +690,14 @@ static void tcp_options_write(__be32 *pt
+@@ -681,13 +687,14 @@ static void tcp_options_write(__be32 *pt
 
  		if (foc->exp) {
  			len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len;
@@ -706,7 +706,7 @@
  EXPORT_SYMBOL(xfrm_parse_spi);
 --- a/net/ipv4/tcp_input.c
 +++ b/net/ipv4/tcp_input.c
-@@ -4138,14 +4138,16 @@ static bool tcp_parse_aligned_timestamp(
+@@ -4140,14 +4140,16 @@ static bool tcp_parse_aligned_timestamp(
  {
  	const __be32 *ptr = (const __be32 *)(th + 1);
 

target/linux/generic/hack-5.15/902-debloat_proc.patch

@@ -341,7 +341,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
 
 --- a/net/ipv4/fib_trie.c
 +++ b/net/ipv4/fib_trie.c
-@@ -3019,11 +3019,13 @@ static const struct seq_operations fib_r
+@@ -3022,11 +3022,13 @@ static const struct seq_operations fib_r
 
  int __net_init fib_proc_init(struct net *net)
  {
@@ -357,7 +357,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
  			fib_triestat_seq_show, NULL))
  		goto out2;
 
-@@ -3034,17 +3036,21 @@ int __net_init fib_proc_init(struct net
+@@ -3037,17 +3039,21 @@ int __net_init fib_proc_init(struct net
  	return 0;
 
  out3:

target/linux/generic/hack-5.18/902-debloat_proc.patch

@@ -341,7 +341,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
 
 --- a/net/ipv4/fib_trie.c
 +++ b/net/ipv4/fib_trie.c
-@@ -3026,11 +3026,13 @@ static const struct seq_operations fib_r
+@@ -3029,11 +3029,13 @@ static const struct seq_operations fib_r
 
  int __net_init fib_proc_init(struct net *net)
  {
@@ -357,7 +357,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
  			fib_triestat_seq_show, NULL))
  		goto out2;
 
-@@ -3041,17 +3043,21 @@ int __net_init fib_proc_init(struct net
+@@ -3044,17 +3046,21 @@ int __net_init fib_proc_init(struct net
  	return 0;
 
  out3:

target/linux/generic/hack-5.19/902-debloat_proc.patch

@@ -341,7 +341,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
 
 --- a/net/ipv4/fib_trie.c
 +++ b/net/ipv4/fib_trie.c
-@@ -3026,11 +3026,13 @@ static const struct seq_operations fib_r
+@@ -3029,11 +3029,13 @@ static const struct seq_operations fib_r
 
  int __net_init fib_proc_init(struct net *net)
  {
@@ -357,7 +357,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
  			fib_triestat_seq_show, NULL))
  		goto out2;
 
-@@ -3041,17 +3043,21 @@ int __net_init fib_proc_init(struct net
+@@ -3044,17 +3046,21 @@ int __net_init fib_proc_init(struct net
  	return 0;
 
  out3:

target/linux/generic/hack-5.19/904-debloat_dma_buf.patch

@@ -64,7 +64,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
 +dma-shared-buffer-objs :=  $(dma-buf-objs-y)
 --- a/drivers/dma-buf/dma-buf.c
 +++ b/drivers/dma-buf/dma-buf.c
-@@ -1459,4 +1459,5 @@ static void __exit dma_buf_deinit(void)
+@@ -1473,4 +1473,5 @@ static void __exit dma_buf_deinit(void)
  	kern_unmount(dma_buf_mnt);
  	dma_buf_uninit_sysfs_statistics();
  }
@@ -73,7 +73,7 @@ Signed-off-by: Felix Fietkau <[email protected]>
 +MODULE_LICENSE("GPL");
 --- a/kernel/sched/core.c
 +++ b/kernel/sched/core.c
-@@ -4287,6 +4287,7 @@ int wake_up_state(struct task_struct *p,
+@@ -4284,6 +4284,7 @@ int wake_up_state(struct task_struct *p,
  {
  	return try_to_wake_up(p, state, 0);
  }

target/linux/generic/hack-5.19/952-add-net-conntrack-events-support-multiple-registrant.patch

@@ -22,7 +22,7 @@ Signed-off-by: Zhi Chen <[email protected]>
 
 --- a/include/net/netfilter/nf_conntrack_ecache.h
 +++ b/include/net/netfilter/nf_conntrack_ecache.h
-@@ -81,9 +81,14 @@ struct nf_ct_event_notifier {
+@@ -65,9 +65,14 @@ struct nf_ct_event_notifier {
  	int (*exp_event)(unsigned int events, const struct nf_exp_event *item);
  };
 
@@ -38,7 +38,7 @@ Signed-off-by: Zhi Chen <[email protected]>
 
  void nf_ct_deliver_cached_events(struct nf_conn *ct);
  int nf_conntrack_eventmask_report(unsigned int eventmask, struct nf_conn *ct,
-@@ -109,11 +114,13 @@ static inline void
+@@ -98,11 +103,13 @@ static inline void
  nf_conntrack_event_cache(enum ip_conntrack_events event, struct nf_conn *ct)
  {
  #ifdef CONFIG_NF_CONNTRACK_EVENTS
@@ -53,7 +53,7 @@ Signed-off-by: Zhi Chen <[email protected]>
 
  	e = nf_ct_ecache_find(ct);
  	if (e == NULL)
-@@ -117,20 +124,24 @@
+@@ -117,20 +124,24 @@ nf_conntrack_event_report(enum ip_conntr
  			  u32 portid, int report)
  {
  #ifdef CONFIG_NF_CONNTRACK_EVENTS
@@ -80,9 +80,9 @@ Signed-off-by: Zhi Chen <[email protected]>
  #ifdef CONFIG_NF_CONNTRACK_EVENTS
 --- a/include/net/netns/conntrack.h
 +++ b/include/net/netns/conntrack.h
-@@ -112,6 +112,9 @@ struct netns_ct {
+@@ -107,6 +107,9 @@ struct netns_ct {
+ 	u8			sysctl_checksum;
 
- 	struct ct_pcpu __percpu *pcpu_lists;
  	struct ip_conntrack_stat __percpu *stat;
 +#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
 +	struct atomic_notifier_head nf_conntrack_chain;
@@ -109,7 +109,7 @@ Signed-off-by: Zhi Chen <[email protected]>
  	depends on NETFILTER_ADVANCED
 --- a/net/netfilter/nf_conntrack_core.c
 +++ b/net/netfilter/nf_conntrack_core.c
-@@ -2837,6 +2837,10 @@ int nf_conntrack_init_net(struct net *ne
+@@ -2802,6 +2802,10 @@ int nf_conntrack_init_net(struct net *ne
  	nf_conntrack_helper_pernet_init(net);
  	nf_conntrack_proto_pernet_init(net);
 
@@ -305,7 +305,7 @@ Signed-off-by: Zhi Chen <[email protected]>
  	struct nf_conn *ct = item->ct;
  	struct sk_buff *skb;
  	unsigned int type;
-@@ -3825,11 +3832,17 @@ static int ctnetlink_stat_exp_cpu(struct
+@@ -3791,11 +3798,17 @@ static int ctnetlink_stat_exp_cpu(struct
  }
 
  #ifdef CONFIG_NF_CONNTRACK_EVENTS
@@ -323,7 +323,7 @@ Signed-off-by: Zhi Chen <[email protected]>
 
  static const struct nfnl_callback ctnl_cb[IPCTNL_MSG_MAX] = {
  	[IPCTNL_MSG_CT_NEW]	= {
-@@ -3928,8 +3941,12 @@ static int __net_init ctnetlink_net_init
+@@ -3894,8 +3907,12 @@ static int __net_init ctnetlink_net_init
  static void ctnetlink_net_pre_exit(struct net *net)
  {
  #ifdef CONFIG_NF_CONNTRACK_EVENTS

target/linux/generic/hack-5.19/953-net-patch-linux-kernel-to-support-shortcut-fe.patch

@@ -12,7 +12,7 @@
  			       struct list_head *br_ip_list);
 --- a/include/linux/skbuff.h
 +++ b/include/linux/skbuff.h
-@@ -1022,6 +1022,10 @@ struct sk_buff {
+@@ -1146,6 +1146,10 @@ struct sk_buff {
  	__u8			slow_gro:1;
  	__u8			csum_not_inet:1;
 
@@ -38,7 +38,7 @@
  #endif
 --- a/include/net/netfilter/nf_conntrack_ecache.h
 +++ b/include/net/netfilter/nf_conntrack_ecache.h
-@@ -84,6 +84,8 @@ struct nf_ct_event_notifier {
+@@ -68,6 +68,8 @@ struct nf_ct_event_notifier {
  #ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
  extern int nf_conntrack_register_notifier(struct net *net, struct notifier_block *nb);
  extern int nf_conntrack_unregister_notifier(struct net *net, struct notifier_block *nb);
@@ -92,7 +92,7 @@
  	struct net_bridge_port *p;
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -3532,9 +3532,17 @@ static int xmit_one(struct sk_buff *skb,
+@@ -3581,9 +3581,17 @@ static int xmit_one(struct sk_buff *skb,
  {
  	unsigned int len;
  	int rc;
@@ -110,8 +110,8 @@
 +#endif
 
  	len = skb->len;
- 	PRANDOM_ADD_NOISE(skb, dev, txq, len + jiffies);
-@@ -5161,6 +5169,11 @@ void netdev_rx_handler_unregister(struct
+ 	trace_net_dev_start_xmit(skb, dev);
+@@ -5232,6 +5240,11 @@ void netdev_rx_handler_unregister(struct
  }
  EXPORT_SYMBOL_GPL(netdev_rx_handler_unregister);
 
@@ -123,7 +123,7 @@
  /*
   * Limit the use of PFMEMALLOC reserves to those protocols that implement
   * the special handling of PFMEMALLOC skbs.
-@@ -5209,6 +5222,10 @@ static int __netif_receive_skb_core(stru
+@@ -5280,6 +5293,10 @@ static int __netif_receive_skb_core(stru
  	int ret = NET_RX_DROP;
  	__be16 type;
 
@@ -134,7 +134,7 @@
  	net_timestamp_check(!netdev_tstamp_prequeue, skb);
 
  	trace_netif_receive_skb(skb);
-@@ -5246,6 +5263,15 @@ another_round:
+@@ -5317,6 +5334,15 @@ another_round:
  			goto out;
  	}
 

target/linux/generic/pending-5.10/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch

@@ -71,7 +71,7 @@ Signed-off-by: Tobias Wolf <[email protected]>
 
 --- a/mm/page_alloc.c
 +++ b/mm/page_alloc.c
-@@ -7055,7 +7055,7 @@ static void __ref alloc_node_mem_map(str
+@@ -7059,7 +7059,7 @@ static void __ref alloc_node_mem_map(str
  	if (pgdat == NODE_DATA(0)) {
  		mem_map = NODE_DATA(0)->node_mem_map;
  		if (page_to_pfn(mem_map) != pgdat->node_start_pfn)

target/linux/generic/pending-5.15/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch

@@ -71,7 +71,7 @@ Signed-off-by: Tobias Wolf <[email protected]>
 
 --- a/mm/page_alloc.c
 +++ b/mm/page_alloc.c
-@@ -7552,7 +7552,7 @@ static void __init alloc_node_mem_map(st
+@@ -7556,7 +7556,7 @@ static void __init alloc_node_mem_map(st
  	if (pgdat == NODE_DATA(0)) {
  		mem_map = NODE_DATA(0)->node_mem_map;
  		if (page_to_pfn(mem_map) != pgdat->node_start_pfn)

target/linux/generic/pending-5.15/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch

@@ -66,7 +66,7 @@ Signed-off-by: Jonas Gorski <[email protected]>
  static void rt_fibinfo_free(struct rtable __rcu **rtp)
 --- a/net/ipv4/fib_trie.c
 +++ b/net/ipv4/fib_trie.c
-@@ -2767,6 +2767,7 @@ static const char *const rtn_type_names[
+@@ -2770,6 +2770,7 @@ static const char *const rtn_type_names[
  	[RTN_THROW] = "THROW",
  	[RTN_NAT] = "NAT",
  	[RTN_XRESOLVE] = "XRESOLVE",

target/linux/generic/pending-5.18/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch

@@ -71,7 +71,7 @@ Signed-off-by: Tobias Wolf <[email protected]>
 
 --- a/mm/page_alloc.c
 +++ b/mm/page_alloc.c
-@@ -7668,7 +7668,7 @@ static void __init alloc_node_mem_map(st
+@@ -7672,7 +7672,7 @@ static void __init alloc_node_mem_map(st
  	if (pgdat == NODE_DATA(0)) {
  		mem_map = NODE_DATA(0)->node_mem_map;
  		if (page_to_pfn(mem_map) != pgdat->node_start_pfn)

target/linux/generic/pending-5.18/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch

@@ -66,7 +66,7 @@ Signed-off-by: Jonas Gorski <[email protected]>
  static void rt_fibinfo_free(struct rtable __rcu **rtp)
 --- a/net/ipv4/fib_trie.c
 +++ b/net/ipv4/fib_trie.c
-@@ -2773,6 +2773,7 @@ static const char *const rtn_type_names[
+@@ -2776,6 +2776,7 @@ static const char *const rtn_type_names[
  	[RTN_THROW] = "THROW",
  	[RTN_NAT] = "NAT",
  	[RTN_XRESOLVE] = "XRESOLVE",

target/linux/generic/pending-5.19/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch

@@ -71,7 +71,7 @@ Signed-off-by: Tobias Wolf <[email protected]>
 
 --- a/mm/page_alloc.c
 +++ b/mm/page_alloc.c
-@@ -7698,7 +7698,7 @@ static void __init alloc_node_mem_map(st
+@@ -7702,7 +7702,7 @@ static void __init alloc_node_mem_map(st
  	if (pgdat == NODE_DATA(0)) {
  		mem_map = NODE_DATA(0)->node_mem_map;
  		if (page_to_pfn(mem_map) != pgdat->node_start_pfn)

target/linux/generic/pending-5.19/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch

@@ -66,7 +66,7 @@ Signed-off-by: Jonas Gorski <[email protected]>
  static void rt_fibinfo_free(struct rtable __rcu **rtp)
 --- a/net/ipv4/fib_trie.c
 +++ b/net/ipv4/fib_trie.c
-@@ -2773,6 +2773,7 @@ static const char *const rtn_type_names[
+@@ -2776,6 +2776,7 @@ static const char *const rtn_type_names[
  	[RTN_THROW] = "THROW",
  	[RTN_NAT] = "NAT",
  	[RTN_XRESOLVE] = "XRESOLVE",

target/linux/rockchip/Makefile

@@ -7,8 +7,8 @@ BOARDNAME:=Rockchip
 FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs
 SUBTARGETS:=armv8
 
-KERNEL_PATCHVER=5.18
-KERNEL_TESTING_PATCHVER=5.4
+KERNEL_PATCHVER=5.15
+KERNEL_TESTING_PATCHVER=5.19
 
 define Target/Description
 	Build firmware image for Rockchip SoC devices.

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts

@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
+ */
+
+/dts-v1/;
+
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+	model = "FriendlyElec NanoPi R2C";
+	compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
+};
+
+&gmac2io {
+	phy-handle = <&yt8521s>;
+
+	mdio {
+		/delete-node/ ethernet-phy@1;
+
+		yt8521s: ethernet-phy@3 {
+			compatible = "ethernet-phy-id0000.011a",
+				     "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+			pinctrl-0 = <&eth_phy_reset_pin>;
+			pinctrl-names = "default";
+			reset-assert-us = <10000>;
+			reset-deassert-us = <50000>;
+			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&lan_led {
+	label = "nanopi-r2c:green:lan";
+};
+
+&sys_led {
+	label = "nanopi-r2c:red:sys";
+};
+
+&wan_led {
+	label = "nanopi-r2c:green:wan";
+};

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts

@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include "rk3328-orangepi-r1-plus.dts"
+
+/ {
+	model = "Xunlong Orange Pi R1 Plus LTS";
+	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
+};
+
+/delete-node/ &rtl8211e;
+&gmac2io {
+        phy-handle = <&ethphy3>;
+        snps,reset-delays-us = <0 15000 50000>;
+        tx_delay = <0x19>;
+        rx_delay = <0x05>;
+        status = "okay";
+
+        mdio {
+                compatible = "snps,dwmac-mdio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ethphy3: ethernet-phy@0 {
+                        reg = <0x0>;
+                        keep-clkout-on;
+                       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+
+&sdmmc {
+      bus-width = <4>;
+      cap-sd-highspeed;
+      disable-wp;
+      pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
+      pinctrl-names = "default";
+      sd-uhs-sdr12;
+      sd-uhs-sdr25;
+      sd-uhs-sdr50;
+      sd-uhs-sdr104;
+      vmmc-supply = <&vcc_sd>;
+      vqmmc-supply = <&vcc_io_sdio>;
+      status = "okay";
+};
+
+&dmc_opp_table {
+        opp-1056000000 {
+                status = "disabled";
+        };
+        opp-924000000 {
+                status = "disabled";
+        };
+        opp-840000000 {
+                status = "disabled";
+        };
+        opp-798000000 {
+                status = "disabled";
+        };
+};
+
+&sys_led {
+       label = "orangepi-r1-plus-lts:red:sys";
+};
+
+&wan_led {
+       label = "orangepi-r1-plus-lts:green:wan";
+};
+
+&lan_led {
+       label = "orangepi-r1-plus-lts:green:lan";
+};

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts

@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+	model = "Xunlong Orange Pi R1 Plus";
+	compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
+};
+
+&lan_led {
+	label = "orangepi-r1-plus:green:lan";
+};
+
+&spi0 {
+	max-freq = <48000000>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+&sys_led {
+	gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+	label = "orangepi-r1-plus:red:sys";
+};
+
+&sys_led_pin {
+	rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&wan_led {
+	label = "orangepi-r1-plus:green:wan";
+};

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dts

@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3399-doornet2.dtsi"
+
+/ {
+	model = "EmbedFire DoorNet2 1GB";
+	compatible = "embedfire,doornet2", "rockchip,rk3399";
+
+	aliases {
+		led-boot = &sys_led;
+		led-failsafe = &sys_led;
+		led-running = &sys_led;
+		led-upgrade = &sys_led;
+	};
+
+	/delete-node/ display-subsystem;
+
+	gpio-leds {
+		pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
+
+		/delete-node/ status;
+
+		lan_led: led-lan {
+			gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
+			label = "green:lan";
+		};
+
+		sys_led: led-sys {
+			gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+			label = "red:sys";
+			default-state = "on";
+		};
+
+		wan_led: led-wan {
+			gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+			label = "green:wan";
+		};
+	};
+
+	gpio-keys {
+		pinctrl-0 = <&reset_button_pin>;
+
+		/delete-node/ power;
+
+		reset {
+			debounce-interval = <50>;
+			gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	vdd_5v: vdd-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_5v";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&pcie0 {
+	max-link-speed = <1>;
+	num-lanes = <1>;
+	vpcie3v3-supply = <&vcc3v3_sys>;
+
+	pcie@0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		pcie-eth@0,0 {
+			compatible = "realtek,r8168";
+			reg = <0x000000 0 0 0 0>;
+
+			realtek,led-data = <0x870>;
+		};
+	};
+};
+
+&pinctrl {
+	gpio-leds {
+		/delete-node/ leds-gpio;
+
+		lan_led_pin: lan-led-pin {
+			rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		sys_led_pin: sys-led-pin {
+			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wan_led_pin: wan-led-pin {
+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rockchip-key {
+		/delete-node/ power-key;
+
+		reset_button_pin: reset-button-pin {
+			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&u2phy0_host {
+	phy-supply = <&vdd_5v>;
+};
+
+&vcc3v3_sys {
+	vin-supply = <&vcc5v0_sys>;
+};

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi

@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * Copyright (c) 2020 Tianling Shen <cnsztl@gmail.com>
+ * Copyright (c) 2020 gzelvis <gzelvis@gmail.com>
+ */
+
+/ {
+	cluster0_opp: opp-table-0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <40000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <800000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <850000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <925000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1000000>;
+		};
+		opp05 {
+			opp-hz = /bits/ 64 <1416000000>;
+			opp-microvolt = <1125000>;
+		};
+		opp06 {
+			opp-hz = /bits/ 64 <1608000000>;
+			opp-microvolt = <1225000>;
+		};
+		opp07 {
+			opp-hz = /bits/ 64 <1800000000>;
+			opp-microvolt = <1275000>;
+		};
+	};
+
+	cluster1_opp: opp-table-1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <40000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <800000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <825000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <875000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <950000>;
+		};
+		opp05 {
+			opp-hz = /bits/ 64 <1416000000>;
+			opp-microvolt = <1025000>;
+		};
+		opp06 {
+			opp-hz = /bits/ 64 <1608000000>;
+			opp-microvolt = <1100000>;
+		};
+		opp07 {
+			opp-hz = /bits/ 64 <1800000000>;
+			opp-microvolt = <1200000>;
+		};
+		opp08 {
+			opp-hz = /bits/ 64 <2016000000>;
+			opp-microvolt = <1250000>;
+		};
+		opp09 {
+			opp-hz = /bits/ 64 <2208000000>;
+			opp-microvolt = <1325000>;
+		};
+	};
+
+	gpu_opp_table: opp-table-2 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <800000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <297000000>;
+			opp-microvolt = <800000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <825000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <875000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <925000>;
+		};
+		opp05 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1100000>;
+		};
+	};
+};
+
+&cpu_l0 {
+	operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l1 {
+	operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l2 {
+	operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l3 {
+	operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_b0 {
+	operating-points-v2 = <&cluster1_opp>;
+};
+
+&cpu_b1 {
+	operating-points-v2 = <&cluster1_opp>;
+};
+
+&gpu {
+	operating-points-v2 = <&gpu_opp_table>;
+};

target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
+ * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
+ */
+
+/* TODO
+ * Delete this file and migrate RockPi 4 to RockPi 4A after
+ * removing Kernel 5.4.
+ */
+
+
+/dts-v1/;
+#include "rk3399-rock-pi-4.dtsi"
+
+/ {
+	model = "Radxa ROCK Pi 4";
+	compatible = "radxa,rockpi4", "rockchip,rk3399";
+};

target/linux/rockchip/patches-5.19/0000-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch

@@ -0,0 +1,31 @@
+From af20b3384e8723077cc6484160b0cf4e9be321de Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Mon, 7 Jun 2021 15:45:37 +0800
+Subject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S
+
+NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which
+stores the MAC address.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+@@ -68,6 +68,15 @@
+ 	status = "disabled";
+ };
+
++&i2c2 {
++	eeprom@51 {
++		compatible = "microchip,24c02", "atmel,24c02";
++		reg = <0x51>;
++		pagesize = <16>;
++		read-only; /* This holds our MAC */
++	};
++};
++
+ &i2c4 {
+ 	status = "disabled";
+ };

target/linux/rockchip/patches-5.19/0001-arm64-dts-rockchip-add-Quartz64-A-fan-pinctrl.patch

@@ -0,0 +1,39 @@
+From 2c26cd88f13382b6965bbf5a8fc1c56384c6c3f6 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Wed, 11 May 2022 11:01:15 -0400
+Subject: [PATCH 01/51] arm64: dts: rockchip: add Quartz64-A fan pinctrl
+
+The Quartz64 Model A fan is bound to a single gpio. Prevent pinctrl
+issues in the future by binding the pinctrl assignment for the gpio.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+Link: https://lore.kernel.org/r/20220511150117.113070-5-pgwipeout@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+@@ -32,6 +32,8 @@
+ 		gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ 		gpio-fan,speed-map = <0    0
+ 				      4500 1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&fan_en_h>;
+ 		#cooling-cells = <2>;
+ 	};
+
+@@ -524,6 +526,12 @@
+ 		};
+ 	};
+
++	fan {
++		fan_en_h: fan-en-h {
++			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	leds {
+ 		work_led_enable_h: work-led-enable-h {
+ 			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;

target/linux/rockchip/patches-5.19/0002-arm64-dts-rockchip-enable-sdr-104-for-sdmmc-on-Quart.patch

@@ -0,0 +1,32 @@
+From eda045fa2ca7b1567457048a389cda854a3a01e5 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Wed, 11 May 2022 11:01:16 -0400
+Subject: [PATCH 02/51] arm64: dts: rockchip: enable sdr-104 for sdmmc on
+ Quartz A
+
+Now that we have working io-domain support, we can enable higher date
+rates on the sdmmc card.
+
+Before:
+Timing buffered disk reads:  68 MB in  3.08 seconds =  22.07 MB/sec
+
+After:
+Timing buffered disk reads: 188 MB in  3.02 seconds =  62.29 MB/sec
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+Link: https://lore.kernel.org/r/20220511150117.113070-6-pgwipeout@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+@@ -596,6 +596,7 @@
+ 	disable-wp;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
++	sd-uhs-sdr104;
+ 	vmmc-supply = <&vcc3v3_sd>;
+ 	vqmmc-supply = <&vccio_sd>;
+ 	status = "okay";

target/linux/rockchip/patches-5.19/0003-arm64-dts-rockchip-enable-sfc-controller-on-Quartz64.patch

@@ -0,0 +1,41 @@
+From 591f44f27342906ccd58eb7e63ec3ef5810bd7eb Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Wed, 11 May 2022 11:01:17 -0400
+Subject: [PATCH 03/51] arm64: dts: rockchip: enable sfc controller on Quartz64
+ Model A
+
+Add the sfc controller binding for the Quartz64 Model A. This is not
+populated by default, so leave it disabled.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+Link: https://lore.kernel.org/r/20220511150117.113070-7-pgwipeout@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3566-quartz64-a.dts      | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+@@ -617,6 +617,22 @@
+ 	status = "okay";
+ };
+
++&sfc {
++	pinctrl-0 = <&fspi_pins>;
++	pinctrl-names = "default";
++	#address-cells = <1>;
++	#size-cells = <0>;
++	status = "disabled";
++
++	flash@0 {
++		compatible = "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <24000000>;
++		spi-rx-bus-width = <4>;
++		spi-tx-bus-width = <1>;
++	};
++};
++
+ /* spdif is exposed on con40 pin 18 */
+ &spdif {
+ 	status = "okay";

target/linux/rockchip/patches-5.19/0004-arm64-dts-rockchip-Add-rk3568-PCIe2x1-controller.patch

@@ -0,0 +1,74 @@
+From 83729931332a2f15b0452f7dc8ea7a2e1b431842 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Fri, 29 Apr 2022 08:38:30 -0400
+Subject: [PATCH 04/51] arm64: dts: rockchip: Add rk3568 PCIe2x1 controller
+
+The PCIe2x1 controller is common between the rk3568 and rk3566. It is a
+single lane PCIe2 compliant controller.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+Link: https://lore.kernel.org/r/20220429123832.2376381-5-pgwipeout@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 50 ++++++++++++++++++++++++
+ 1 file changed, 50 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -752,6 +752,56 @@
+ 		reg = <0x0 0xfe1a8100 0x0 0x20>;
+ 	};
+
++	pcie2x1: pcie@fe260000 {
++		compatible = "rockchip,rk3568-pcie";
++		reg = <0x3 0xc0000000 0x0 0x00400000>,
++		      <0x0 0xfe260000 0x0 0x00010000>,
++		      <0x3 0x3f000000 0x0 0x01000000>;
++		reg-names = "dbi", "apb", "config";
++		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
++			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
++			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
++			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "sys", "pmc", "msi", "legacy", "err";
++		bus-range = <0x0 0xf>;
++		clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
++			 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
++			 <&cru CLK_PCIE20_AUX_NDFT>;
++		clock-names = "aclk_mst", "aclk_slv",
++			      "aclk_dbi", "pclk", "aux";
++		device_type = "pci";
++		interrupt-map-mask = <0 0 0 7>;
++		interrupt-map = <0 0 0 1 &pcie_intc 0>,
++				<0 0 0 2 &pcie_intc 1>,
++				<0 0 0 3 &pcie_intc 2>,
++				<0 0 0 4 &pcie_intc 3>;
++		linux,pci-domain = <0>;
++		num-ib-windows = <6>;
++		num-ob-windows = <2>;
++		max-link-speed = <2>;
++		msi-map = <0x0 &gic 0x0 0x1000>;
++		num-lanes = <1>;
++		phys = <&combphy2 PHY_TYPE_PCIE>;
++		phy-names = "pcie-phy";
++		power-domains = <&power RK3568_PD_PIPE>;
++		ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
++			  0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
++		resets = <&cru SRST_PCIE20_POWERUP>;
++		reset-names = "pipe";
++		#address-cells = <3>;
++		#size-cells = <2>;
++		status = "disabled";
++
++		pcie_intc: legacy-interrupt-controller {
++			#address-cells = <0>;
++			#interrupt-cells = <1>;
++			interrupt-controller;
++			interrupt-parent = <&gic>;
++			interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
++		};
++	};
++
+ 	sdmmc0: mmc@fe2b0000 {
+ 		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+ 		reg = <0x0 0xfe2b0000 0x0 0x4000>;

target/linux/rockchip/patches-5.19/0005-arm64-dts-rockchip-Enable-PCIe-controller-on-quartz6.patch

@@ -0,0 +1,80 @@
+From 5b1b78762d3fb4cf20aec4b22fbfab33960a6fdc Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Fri, 29 Apr 2022 08:38:31 -0400
+Subject: [PATCH 05/51] arm64: dts: rockchip: Enable PCIe controller on
+ quartz64-a
+
+Add the nodes to enable the PCIe controller on the Quartz64 Model A
+board.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+Link: https://lore.kernel.org/r/20220429123832.2376381-6-pgwipeout@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 34 +++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+@@ -127,6 +127,18 @@
+ 		vin-supply = <&vcc12v_dcin>;
+ 	};
+
++	vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pcie_enable_h>;
++		regulator-name = "vcc3v3_pcie_p";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc_3v3>;
++	};
++
+ 	vcc5v0_usb: vcc5v0_usb {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc5v0_usb";
+@@ -203,6 +215,10 @@
+ 	status = "okay";
+ };
+
++&combphy2 {
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&vdd_cpu>;
+ };
+@@ -511,6 +527,14 @@
+ 	};
+ };
+
++&pcie2x1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_reset_h>;
++	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pcie_p>;
++	status = "okay";
++};
++
+ &pinctrl {
+ 	bt {
+ 		bt_enable_h: bt-enable-h {
+@@ -542,6 +566,16 @@
+ 		};
+ 	};
+
++	pcie {
++		pcie_enable_h: pcie-enable-h {
++			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		pcie_reset_h: pcie-reset-h {
++			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	pmic {
+ 		pmic_int_l: pmic-int-l {
+ 			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;

target/linux/rockchip/patches-5.19/0006-arm64-dts-rockchip-add-pine64-touch-panel-display-to.patch

@@ -0,0 +1,131 @@
+From 175ce006fe4ebf077322e5818127acfade41296f Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Wed, 11 May 2022 07:35:16 -0400
+Subject: [PATCH 06/51] arm64: dts: rockchip: add pine64 touch panel display to
+ rockpro64
+
+The Pine64 touch panel is a panel consisting of the Feiyang fy07024di26a30d
+panel with a Goodix gt911 touch screen. Add the device tree nodes to the
+rockpro64 to permit attaching this display to the device.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+Link: https://lore.kernel.org/r/20220511113517.4172962-4-pgwipeout@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3399-rockpro64.dtsi   | 70 +++++++++++++++++--
+ 1 file changed, 66 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+@@ -20,6 +20,15 @@
+ 		stdout-path = "serial2:1500000n8";
+ 	};
+
++	/* enable for panel backlight support */
++	backlight: backlight {
++		compatible = "pwm-backlight";
++		brightness-levels = <0 4 8 16 32 64 128 255>;
++		default-brightness-level = <5>;
++		pwms = <&pwm0 0 1000000 0>;
++		status = "disabled";
++	};
++
+ 	clkin_gmac: external-gmac-clock {
+ 		compatible = "fixed-clock";
+ 		clock-frequency = <125000000>;
+@@ -107,6 +116,14 @@
+ 		};
+ 	};
+
++	avdd: avdd-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "avdd";
++		regulator-min-microvolt = <11000000>;
++		regulator-max-microvolt = <11000000>;
++		vin-supply = <&vcc3v3_s0>;
++	};
++
+ 	vcc12v_dcin: vcc12v-dcin {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc12v_dcin";
+@@ -400,8 +417,6 @@
+
+ 			vcc3v0_touch: LDO_REG2 {
+ 				regulator-name = "vcc3v0_touch";
+-				regulator-always-on;
+-				regulator-boot-on;
+ 				regulator-min-microvolt = <3000000>;
+ 				regulator-max-microvolt = <3000000>;
+ 				regulator-state-mem {
+@@ -490,8 +505,6 @@
+
+ 			vcc3v3_s0: SWITCH_REG2 {
+ 				regulator-name = "vcc3v3_s0";
+-				regulator-always-on;
+-				regulator-boot-on;
+ 				regulator-state-mem {
+ 					regulator-off-in-suspend;
+ 				};
+@@ -565,6 +578,19 @@
+ 		vbus-supply = <&vcc5v0_typec>;
+ 		status = "okay";
+ 	};
++
++	/* enable for pine64 touch screen support */
++	touch: touchscreen@5d {
++		compatible = "goodix,gt911";
++		reg = <0x5d>;
++		interrupt-parent = <&gpio4>;
++		interrupts = <RK_PD5 IRQ_TYPE_EDGE_FALLING>;
++		AVDD28-supply = <&vcc3v0_touch>;
++		VDDIO-supply = <&vcc3v0_touch>;
++		irq-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
++		reset-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
++		status = "disabled";
++	};
+ };
+
+ &i2s0 {
+@@ -600,6 +626,42 @@
+ 	gpio1830-supply = <&vcc_3v0>;
+ };
+
++/* enable for pine64 panel display support */
++&mipi_dsi {
++	clock-master;
++	status = "disabled";
++
++	ports {
++		mipi_out: port@1 {
++			reg = <1>;
++
++			mipi_out_panel: endpoint {
++				remote-endpoint = <&mipi_in_panel>;
++			};
++		};
++	};
++
++	mipi_panel: panel@0 {
++		compatible = "feiyang,fy07024di26a30d";
++		reg = <0>;
++		avdd-supply = <&avdd>;
++		backlight = <&backlight>;
++		dvdd-supply = <&vcc3v3_s0>;
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@0 {
++				reg = <0>;
++
++				mipi_in_panel: endpoint {
++					remote-endpoint = <&mipi_out_panel>;
++				};
++			};
++		};
++	};
++};
++
+ &pcie0 {
+ 	ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
+ 	num-lanes = <4>;

target/linux/rockchip/patches-5.19/0007-arm64-dts-rockchip-rk356x-Add-VOP2-nodes.patch

@@ -0,0 +1,106 @@
+From ec7cbc7e9111d3d655f25807e8511492359bb0fd Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Fri, 22 Apr 2022 09:28:33 +0200
+Subject: [PATCH 07/51] arm64: dts: rockchip: rk356x: Add VOP2 nodes
+
+The VOP2 is the display output controller on the RK3568. Add the node
+for it to the dtsi file along with the required display-subsystem node
+and the iommu node.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Acked-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20220422072841.2206452-17-s.hauer@pengutronix.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566.dtsi |  4 ++
+ arch/arm64/boot/dts/rockchip/rk3568.dtsi |  4 ++
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 51 ++++++++++++++++++++++++
+ 3 files changed, 59 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
+@@ -29,3 +29,7 @@
+ 	extcon = <&usb2phy0>;
+ 	maximum-speed = "high-speed";
+ };
++
++&vop {
++	compatible = "rockchip,rk3566-vop";
++};
+--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+@@ -137,3 +137,7 @@
+ 	phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
+ 	phy-names = "usb2-phy", "usb3-phy";
+ };
++
++&vop {
++	compatible = "rockchip,rk3568-vop";
++};
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -129,6 +129,11 @@
+ 		};
+ 	};
+
++	display_subsystem: display-subsystem {
++		compatible = "rockchip,display-subsystem";
++		ports = <&vop_out>;
++	};
++
+ 	firmware {
+ 		scmi: scmi {
+ 			compatible = "arm,scmi-smc";
+@@ -632,6 +637,52 @@
+ 		};
+ 	};
+
++	vop: vop@fe040000 {
++		reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
++		reg-names = "vop", "gamma-lut";
++		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
++			 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
++		clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
++		iommus = <&vop_mmu>;
++		power-domains = <&power RK3568_PD_VO>;
++		rockchip,grf = <&grf>;
++		status = "disabled";
++
++		vop_out: ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			vp0: port@0 {
++				reg = <0>;
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
++
++			vp1: port@1 {
++				reg = <1>;
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
++
++			vp2: port@2 {
++				reg = <2>;
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
++		};
++	};
++
++	vop_mmu: iommu@fe043e00 {
++		compatible = "rockchip,rk3568-iommu";
++		reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
++		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
++		clock-names = "aclk", "iface";
++		#iommu-cells = <0>;
++		status = "disabled";
++	};
++
+ 	qos_gpu: qos@fe128000 {
+ 		compatible = "rockchip,rk3568-qos", "syscon";
+ 		reg = <0x0 0xfe128000 0x0 0x20>;

target/linux/rockchip/patches-5.19/0008-arm64-dts-rockchip-rk356x-Add-HDMI-nodes.patch

@@ -0,0 +1,56 @@
+From 98180f4652c2c994cc2cc6088932086ee5c6e4d9 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Fri, 22 Apr 2022 09:28:34 +0200
+Subject: [PATCH 08/51] arm64: dts: rockchip: rk356x: Add HDMI nodes
+
+Add support for the HDMI port found on RK3568.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Link: https://lore.kernel.org/r/20220422072841.2206452-18-s.hauer@pengutronix.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 32 ++++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -683,6 +683,38 @@
+ 		status = "disabled";
+ 	};
+
++	hdmi: hdmi@fe0a0000 {
++		compatible = "rockchip,rk3568-dw-hdmi";
++		reg = <0x0 0xfe0a0000 0x0 0x20000>;
++		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru PCLK_HDMI_HOST>,
++			 <&cru CLK_HDMI_SFR>,
++			 <&cru CLK_HDMI_CEC>,
++			 <&pmucru CLK_HDMI_REF>,
++			 <&cru HCLK_VO>;
++		clock-names = "iahb", "isfr", "cec", "ref";
++		pinctrl-names = "default";
++		pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
++		power-domains = <&power RK3568_PD_VO>;
++		reg-io-width = <4>;
++		rockchip,grf = <&grf>;
++		#sound-dai-cells = <0>;
++		status = "disabled";
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			hdmi_in: port@0 {
++				reg = <0>;
++			};
++
++			hdmi_out: port@1 {
++				reg = <1>;
++			};
++		};
++	};
++
+ 	qos_gpu: qos@fe128000 {
+ 		compatible = "rockchip,rk3568-qos", "syscon";
+ 		reg = <0x0 0xfe128000 0x0 0x20>;

target/linux/rockchip/patches-5.19/0009-arm64-dts-rockchip-rk3568-evb-Enable-VOP2-and-hdmi.patch

@@ -0,0 +1,90 @@
+From 7ccf41205a3deb146e7cc4fffb59fb1eb490a649 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Fri, 22 Apr 2022 09:28:35 +0200
+Subject: [PATCH 09/51] arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi
+
+This enabled the VOP2 display controller along with hdmi and the
+required port routes which is enough to get a picture out of the
+hdmi port of the board.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Link: https://lore.kernel.org/r/20220422072841.2206452-19-s.hauer@pengutronix.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3568-evb1-v10.dts     | 47 +++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
+@@ -8,6 +8,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3568.dtsi"
+
+ / {
+@@ -34,6 +35,17 @@
+ 		regulator-max-microvolt = <12000000>;
+ 	};
+
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+
+@@ -209,6 +221,24 @@
+ 	status = "okay";
+ };
+
++&hdmi {
++	avdd-0v9-supply = <&vdda0v9_image>;
++	avdd-1v8-supply = <&vcca1v8_image>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &i2c0 {
+ 	status = "okay";
+
+@@ -635,3 +665,20 @@
+ 	phy-supply = <&vcc5v0_usb_host>;
+ 	status = "okay";
+ };
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};

target/linux/rockchip/patches-5.19/0010-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz.patch

@@ -0,0 +1,91 @@
+From d6eb924b01522decb987cb8c70d66c6b732a91e4 Mon Sep 17 00:00:00 2001
+From: Michael Riesch <michael.riesch@wolfvision.net>
+Date: Fri, 22 Apr 2022 09:28:36 +0200
+Subject: [PATCH 10/51] arm64: dts: rockchip: enable vop2 and hdmi tx on
+ quartz64a
+
+Enable the RK356x Video Output Processor (VOP) 2 on the Pine64
+Quartz64 Model A.
+
+Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Link: https://lore.kernel.org/r/20220422072841.2206452-20-s.hauer@pengutronix.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 47 +++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+@@ -4,6 +4,7 @@
+
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3566.dtsi"
+
+ / {
+@@ -37,6 +38,17 @@
+ 		#cooling-cells = <2>;
+ 	};
+
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+
+@@ -280,6 +292,24 @@
+ 	status = "okay";
+ };
+
++&hdmi {
++	avdd-0v9-supply = <&vdda_0v9>;
++	avdd-1v8-supply = <&vcc_1v8>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &i2c0 {
+ 	status = "okay";
+
+@@ -782,3 +812,20 @@
+ 	phy-supply = <&vcc5v0_usb20_host>;
+ 	status = "okay";
+ };
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};

target/linux/rockchip/patches-5.19/0011-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-rock-3.patch

@@ -0,0 +1,93 @@
+From 284f0150efd541d60156bcfea1d575b24d320cc3 Mon Sep 17 00:00:00 2001
+From: Michael Riesch <michael.riesch@wolfvision.net>
+Date: Fri, 22 Apr 2022 09:28:37 +0200
+Subject: [PATCH 11/51] arm64: dts: rockchip: enable vop2 and hdmi tx on
+ rock-3a
+
+Enable the RK356x Video Output Processor (VOP) 2 on the Radxa
+ROCK3 Model A.
+
+Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
+Reported-by: kernel test robot <lkp@intel.com>
+Link: https://lore.kernel.org/r/20220310210352.451136-4-michael.riesch@wolfvision.net
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Link: https://lore.kernel.org/r/20220422072841.2206452-21-s.hauer@pengutronix.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3568-rock-3a.dts      | 47 +++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -4,6 +4,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3568.dtsi"
+
+ / {
+@@ -20,6 +21,17 @@
+ 		stdout-path = "serial2:1500000n8";
+ 	};
+
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+
+@@ -166,6 +178,24 @@
+ 	status = "okay";
+ };
+
++&hdmi {
++	avdd-0v9-supply = <&vdda0v9_image>;
++	avdd-1v8-supply = <&vcca1v8_image>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &i2c0 {
+ 	status = "okay";
+
+@@ -560,3 +590,20 @@
+ 	phy-supply = <&vcc5v0_usb_host>;
+ 	status = "okay";
+ };
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};

target/linux/rockchip/patches-5.19/0013-arm64-dts-rockchip-adjust-whitespace-around.patch

@@ -0,0 +1,105 @@
+From 6ca0fc50d82e4ee0c1f5a2ba35cc692cfb4eeeec Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Thu, 26 May 2022 22:42:16 +0200
+Subject: [PATCH 13/51] arm64: dts: rockchip: adjust whitespace around '='
+
+Fix whitespace coding style: use single space instead of tabs or
+multiple spaces around '=' sign in property assignment.  No functional
+changes (same DTB).
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20220526204218.832029-1-krzysztof.kozlowski@linaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/px30.dtsi                     | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3368.dtsi                   | 6 +++---
+ arch/arm64/boot/dts/rockchip/rk3399-evb.dts                | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts        | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi      | 2 +-
+ 6 files changed, 8 insertions(+), 8 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
++++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
+@@ -528,7 +528,7 @@
+ 	i2c0: i2c@ff180000 {
+ 		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
+ 		reg = <0x0 0xff180000 0x0 0x1000>;
+-		clocks =  <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
++		clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
+ 		clock-names = "i2c", "pclk";
+ 		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ 		pinctrl-names = "default";
+--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+@@ -1084,7 +1084,7 @@
+
+ 		gmac {
+ 			rgmii_pins: rgmii-pins {
+-				rockchip,pins =	<3 RK_PC6 1 &pcfg_pull_none>,
++				rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
+ 						<3 RK_PD0 1 &pcfg_pull_none>,
+ 						<3 RK_PC3 1 &pcfg_pull_none>,
+ 						<3 RK_PB0 1 &pcfg_pull_none_12ma>,
+@@ -1102,7 +1102,7 @@
+ 			};
+
+ 			rmii_pins: rmii-pins {
+-				rockchip,pins =	<3 RK_PC6 1 &pcfg_pull_none>,
++				rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
+ 						<3 RK_PD0 1 &pcfg_pull_none>,
+ 						<3 RK_PC3 1 &pcfg_pull_none>,
+ 						<3 RK_PB0 1 &pcfg_pull_none_12ma>,
+@@ -1257,7 +1257,7 @@
+
+ 		spdif {
+ 			spdif_tx: spdif-tx {
+-				rockchip,pins =	<2 RK_PC7 1 &pcfg_pull_none>;
++				rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
+ 			};
+ 		};
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
+@@ -55,7 +55,7 @@
+ 	};
+
+ 	edp_panel: edp-panel {
+-		compatible ="lg,lp079qx1-sp0v";
++		compatible = "lg,lp079qx1-sp0v";
+ 		backlight = <&backlight>;
+ 		enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+ 		power-supply = <&vcc3v3_s0>;
+--- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
+@@ -49,7 +49,7 @@
+ 	sgtl5000_clk: sgtl5000-oscillator  {
+ 			compatible = "fixed-clock";
+ 			#clock-cells = <0>;
+-			clock-frequency  = <24576000>;
++			clock-frequency = <24576000>;
+ 	};
+
+ 	dc_12v: dc-12v {
+--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
+@@ -88,7 +88,7 @@
+ 	};
+
+ 	edp_panel: edp-panel {
+-		compatible ="lg,lp079qx1-sp0v";
++		compatible = "lg,lp079qx1-sp0v";
+ 		backlight = <&backlight>;
+ 		enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+ 		pinctrl-names = "default";
+--- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+@@ -347,7 +347,7 @@
+
+ 	pcie {
+ 		pcie_pwr: pcie-pwr {
+-			rockchip,pins =	<4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
++			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+ 		};
+ 	};
+

target/linux/rockchip/patches-5.19/0014-arm64-dts-rockchip-Add-HDMI-audio-nodes-to-rk356x.patch

@@ -0,0 +1,67 @@
+From 7a32752d0d94ea613092aaa45db136626a55a1ab Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Sat, 11 Jun 2022 08:52:59 +0200
+Subject: [PATCH 14/51] arm64: dts: rockchip: Add HDMI audio nodes to rk356x
+
+This adds the i2s0 node and an hdmi-sound sound device to the
+rk356x device tree. On the rk356[68], the i2s0 controller is
+connected to HDMI audio.
+
+Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
+Tested-by: Peter Geis <pgwipeout@gmail.com>
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20220611065300.885212-2-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 33 ++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -183,6 +183,22 @@
+ 		};
+ 	};
+
++	hdmi_sound: hdmi-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "HDMI";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,mclk-fs = <256>;
++		status = "disabled";
++
++		simple-audio-card,codec {
++			sound-dai = <&hdmi>;
++		};
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s0_8ch>;
++		};
++	};
++
+ 	pmu {
+ 		compatible = "arm,cortex-a55-pmu";
+ 		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
+@@ -950,6 +966,23 @@
+ 		#sound-dai-cells = <0>;
+ 		status = "disabled";
+ 	};
++
++	i2s0_8ch: i2s@fe400000 {
++		compatible = "rockchip,rk3568-i2s-tdm";
++		reg = <0x0 0xfe400000 0x0 0x1000>;
++		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
++		assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
++		assigned-clock-rates = <1188000000>, <1188000000>;
++		clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk";
++		dmas = <&dmac1 0>;
++		dma-names = "tx";
++		resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
++		reset-names = "tx-m", "rx-m";
++		rockchip,grf = <&grf>;
++		#sound-dai-cells = <0>;
++		status = "disabled";
++	};
+
+ 	i2s1_8ch: i2s@fe410000 {
+ 		compatible = "rockchip,rk3568-i2s-tdm";

target/linux/rockchip/patches-5.19/0015-arm64-dts-rockchip-Enable-HDMI-audio-on-Quartz64-A.patch

@@ -0,0 +1,40 @@
+From 2d330dcbbb5f3ce5ff55a2642aac4fb0d0e0a79e Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Sat, 11 Jun 2022 08:53:00 +0200
+Subject: [PATCH 15/51] arm64: dts: rockchip: Enable HDMI audio on Quartz64 A
+
+This enables the i2s0 controller and the hdmi-sound node on
+the PINE64 Quartz64 Model A single-board computer.
+
+Tested-by: Peter Geis <pgwipeout@gmail.com>
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20220611065300.885212-3-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+@@ -310,6 +310,10 @@
+ 	};
+ };
+
++&hdmi_sound {
++	status = "okay";
++};
++
+ &i2c0 {
+ 	status = "okay";
+
+@@ -540,6 +544,10 @@
+ 	status = "okay";
+ };
+
++&i2s0_8ch {
++	status = "okay";
++};
++
+ &i2s1_8ch {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&i2s1m0_sclktx

target/linux/rockchip/patches-5.19/0017-arm64-dts-rockchip-add-RTC-to-BPI-R2-Pro.patch

@@ -0,0 +1,53 @@
+From 0a691542952f6706436e383f984c38b361c986ee Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Wed, 8 Jun 2022 18:11:49 +0200
+Subject: [PATCH 17/51] arm64: dts: rockchip: add RTC to BPI-R2 Pro
+
+Add devicetree node for hym8563 rtc to Bananapi R2 Pro board.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20220608161150.58919-3-linux@fw-web.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts   | 23 +++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -389,6 +389,23 @@
+ 	};
+ };
+
++&i2c3 {
++	status = "okay";
++
++	hym8563: rtc@51 {
++		compatible = "haoyu,hym8563";
++		reg = <0x51>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
++		#clock-cells = <0>;
++		clock-frequency = <32768>;
++		clock-output-names = "rtcic_32kout";
++		pinctrl-names = "default";
++		pinctrl-0 = <&hym8563_int>;
++		wakeup-source;
++	};
++};
++
+ &i2c5 {
+ 	/* pin 3 (SDA) + 4 (SCL) of header con2 */
+ 	status = "disabled";
+@@ -411,6 +428,12 @@
+ 		};
+ 	};
+
++	hym8563 {
++		hym8563_int: hym8563-int {
++			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	pmic {
+ 		pmic_int: pmic_int {
+ 			rockchip,pins =

target/linux/rockchip/patches-5.19/0019-arm64-dts-rockchip-set-display-regulators-to-always-.patch

@@ -0,0 +1,44 @@
+From 032baf8d6c3493e0dcad2c780361faa7ac4f9dde Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Mon, 6 Jun 2022 19:07:59 +0200
+Subject: [PATCH 19/51] arm64: dts: rockchip: set display regulators to
+ always-on on BPI-R2-Pro
+
+The gpu power supply needs to stay always on until the issues with power-
+domains not being regulator aware is resolved. Otherwise we run into
+issues where the gpu-regulator gets shut down and we start getting mmu
+faults.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20220606170803.478082-2-linux@fw-web.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -215,6 +215,7 @@
+
+ 			vdd_gpu: DCDC_REG2 {
+ 				regulator-name = "vdd_gpu";
++				regulator-always-on;
+ 				regulator-init-microvolt = <900000>;
+ 				regulator-initial-mode = <0x2>;
+ 				regulator-min-microvolt = <500000>;
+@@ -264,6 +265,7 @@
+
+ 			vdda0v9_image: LDO_REG1 {
+ 				regulator-name = "vdda0v9_image";
++				regulator-always-on;
+ 				regulator-min-microvolt = <900000>;
+ 				regulator-max-microvolt = <900000>;
+
+@@ -359,6 +361,7 @@
+
+ 			vcca1v8_image: LDO_REG9 {
+ 				regulator-name = "vcca1v8_image";
++				regulator-always-on;
+ 				regulator-min-microvolt = <1800000>;
+ 				regulator-max-microvolt = <1800000>;
+

target/linux/rockchip/patches-5.19/0020-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-BPI-R2.patch

@@ -0,0 +1,90 @@
+From ffb2555c106a820acc90d31c201d9879b4400623 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Mon, 6 Jun 2022 19:08:00 +0200
+Subject: [PATCH 20/51] arm64: dts: rockchip: enable vop2 and hdmi tx on
+ BPI-R2-Pro
+
+Enable the RK356x Video Output Processor (VOP) 2 on the
+BananaPi R2 Pro board.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20220606170803.478082-3-linux@fw-web.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts   | 47 +++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -8,6 +8,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3568.dtsi"
+
+ / {
+@@ -54,6 +55,17 @@
+ 		regulator-max-microvolt = <12000000>;
+ 	};
+
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	vcc3v3_sys: vcc3v3-sys {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc3v3_sys";
+@@ -174,6 +186,24 @@
+ 	status = "okay";
+ };
+
++&hdmi {
++	avdd-0v9-supply = <&vdda0v9_image>;
++	avdd-1v8-supply = <&vcca1v8_image>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &i2c0 {
+ 	status = "okay";
+
+@@ -613,3 +643,20 @@
+ 	phy-supply = <&vcc5v0_usb_otg>;
+ 	status = "okay";
+ };
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};

target/linux/rockchip/patches-5.19/0021-arm64-dts-rockchip-Enable-HDMI-audio-on-BPI-R2-Pro.patch

@@ -0,0 +1,40 @@
+From 16fa52e8e2aae8debb651ac5f84a8d49499a301e Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Mon, 6 Jun 2022 19:08:01 +0200
+Subject: [PATCH 21/51] arm64: dts: rockchip: Enable HDMI audio on BPI R2 Pro
+
+This enables the i2s0 controller and the hdmi-sound node on
+the Bananapi R2 Pro single-board computer.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20220606170803.478082-4-linux@fw-web.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -204,6 +204,10 @@
+ 	};
+ };
+
++&hdmi_sound {
++	status = "okay";
++};
++
+ &i2c0 {
+ 	status = "okay";
+
+@@ -444,6 +448,11 @@
+ 	status = "disabled";
+ };
+
++&i2s0_8ch {
++	/* hdmi sound */
++	status = "okay";
++};
++
+ &mdio1 {
+ 	rgmii_phy1: ethernet-phy@0 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";

target/linux/rockchip/patches-5.19/0022-arm64-dts-rockchip-configure-thermal-shutdown-for-BP.patch

@@ -0,0 +1,26 @@
+From 6976a5970ca53ac9dba444f4929528c3400152a5 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Mon, 6 Jun 2022 19:08:02 +0200
+Subject: [PATCH 22/51] arm64: dts: rockchip: configure thermal shutdown for
+ BPI-R2-Pro
+
+Add thermal shutdown configuration for use of GPU.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20220606170803.478082-5-linux@fw-web.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -588,6 +588,8 @@
+ };
+
+ &tsadc {
++	rockchip,hw-tshut-mode = <1>;
++	rockchip,hw-tshut-polarity = <0>;
+ 	status = "okay";
+ };
+

target/linux/rockchip/patches-5.19/0023-arm64-dts-rockchip-enable-the-gpu-on-BPI-R2-Pro.patch

@@ -0,0 +1,28 @@
+From 92e9e89c7fe9178cb56dba0faf4b0fabbc19d97d Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Mon, 6 Jun 2022 19:08:03 +0200
+Subject: [PATCH 23/51] arm64: dts: rockchip: enable the gpu on BPI-R2-Pro
+
+Enable the GPU core on the Rockchip RK3568 BananaPi R2 Pro
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20220606170803.478082-6-linux@fw-web.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -186,6 +186,11 @@
+ 	status = "okay";
+ };
+
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
+ &hdmi {
+ 	avdd-0v9-supply = <&vdda0v9_image>;
+ 	avdd-1v8-supply = <&vcca1v8_image>;

target/linux/rockchip/patches-5.19/0024-arm64-dts-rockchip-Add-missing-space-around-regulato.patch

@@ -0,0 +1,31 @@
+From fe99ab9113e33c825d1efb8d66f79e217e3108bf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Mon, 13 Jun 2022 00:31:57 +0200
+Subject: [PATCH 24/51] arm64: dts: rockchip: Add missing space around
+ regulator-name on rk3368-orion-r68
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add the missing space around the regulator-name property before the typo
+spreads to other files.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Link: https://lore.kernel.org/r/20220612223201.2740248-3-niklas.soderlund+renesas@ragnatech.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
+@@ -134,7 +134,7 @@
+
+ 	vccio_sd: vcc-io-sd-regulator {
+ 		compatible = "regulator-fixed";
+-		regulator-name= "vccio_sd";
++		regulator-name = "vccio_sd";
+ 		regulator-min-microvolt = <1800000>;
+ 		regulator-max-microvolt = <3300000>;
+ 		regulator-always-on;

target/linux/rockchip/patches-5.19/0025-arm64-dts-rockchip-add-ROCK-Pi-S-DTS-support.patch

@@ -0,0 +1,245 @@
+From 50373d43ecd2504c240f0048087bf0a1fd6e8b4c Mon Sep 17 00:00:00 2001
+From: Akash Gajjar <akash@openedev.com>
+Date: Tue, 14 Jun 2022 08:48:56 +0200
+Subject: [PATCH 25/51] arm64: dts: rockchip: add ROCK Pi S DTS support
+
+ROCK Pi S is RK3308 based SBC from radxa.com. ROCK Pi S has a,
+- 256MB/512MB DDR3 RAM
+- SD, NAND flash (optional on board 1/2/4/8Gb)
+- 100MB ethernet, PoE (optional)
+- Onboard 802.11 b/g/n wifi + Bluetooth 4.0 Module
+- USB2.0 Type-A HOST x1
+- USB3.0 Type-C OTG x1
+- 26-pin expansion header
+- USB Type-C DC 5V Power Supply
+
+This patch enables
+- Console
+- NAND Flash
+- SD Card
+
+Signed-off-by: Akash Gajjar <akash@openedev.com>
+[sjoerd: Sort dt nodes, drop properties duplicated from dtsi]
+Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
+Link: https://lore.kernel.org/r/20220614064858.1445817-3-sjoerd@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../boot/dts/rockchip/rk3308-rock-pi-s.dts    | 201 ++++++++++++++++++
+ 2 files changed, 202 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engi
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
+@@ -0,0 +1,201 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2019 Akash Gajjar <akash@openedev.com>
++ * Copyright (c) 2019 Jagan Teki <jagan@openedev.com>
++ */
++
++/dts-v1/;
++#include "rk3308.dtsi"
++
++/ {
++	model = "Radxa ROCK Pi S";
++	compatible = "radxa,rockpis", "rockchip,rk3308";
++
++	chosen {
++		stdout-path = "serial0:1500000n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>;
++
++		green-led {
++			default-state = "on";
++			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++			label = "rockpis:green:power";
++			linux,default-trigger = "default-on";
++		};
++
++		blue-led {
++			default-state = "on";
++			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
++			label = "rockpis:blue:user";
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		pinctrl-0 = <&wifi_enable_h>;
++		pinctrl-names = "default";
++		reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
++	};
++
++	vcc_1v8: vcc-1v8 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_1v8";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc_io>;
++	};
++
++	vcc_io: vcc-io {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_io";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc_ddr: vcc-ddr {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_ddr";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1500000>;
++		regulator-max-microvolt = <1500000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc5v0_otg: vcc5v0-otg {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&otg_vbus_drv>;
++		regulator-name = "vcc5v0_otg";
++		regulator-always-on;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc5v0_sys: vcc5v0-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vdd_core: vdd-core {
++		compatible = "pwm-regulator";
++		pwms = <&pwm0 0 5000 1>;
++		pwm-supply = <&vcc5v0_sys>;
++		regulator-name = "vdd_core";
++		regulator-min-microvolt = <827000>;
++		regulator-max-microvolt = <1340000>;
++		regulator-init-microvolt = <1015000>;
++		regulator-settling-time-up-us = <250>;
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++	vdd_log: vdd-log {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd_log";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1050000>;
++		regulator-max-microvolt = <1050000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_core>;
++};
++
++&emmc {
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	mmc-hs200-1_8v;
++	non-removable;
++	vmmc-supply = <&vcc_io>;
++	status = "okay";
++};
++
++&i2c1 {
++	status = "okay";
++};
++
++&pinctrl {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rtc_32k>;
++
++	leds {
++		green_led_gio: green-led-gpio {
++			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		heartbeat_led_gpio: heartbeat-led-gpio {
++			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb {
++		otg_vbus_drv: otg-vbus-drv {
++			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		wifi_host_wake: wifi-host-wake {
++			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++};
++
++&pwm0 {
++	status = "okay";
++	pinctrl-0 = <&pwm0_pin_pull_down>;
++};
++
++&saradc {
++	vref-supply = <&vcc_1v8>;
++	status = "okay";
++};
++
++&sdio {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	keep-power-in-suspend;
++	max-frequency = <1000000>;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	sd-uhs-sdr104;
++	status = "okay";
++};
++
++&sdmmc {
++	cap-sd-highspeed;
++	status = "okay";
++};
++
++&uart0 {
++	status = "okay";
++};
++
++&uart4 {
++	status = "okay";
++};

target/linux/rockchip/patches-5.19/0026-arm64-dts-rockchip-rock-pi-s-add-more-peripherals.patch

@@ -0,0 +1,100 @@
+From a1bee6a014cf68d8298c370115f7036f0dcb4f59 Mon Sep 17 00:00:00 2001
+From: Sjoerd Simons <sjoerd@collabora.com>
+Date: Tue, 14 Jun 2022 08:48:57 +0200
+Subject: [PATCH 26/51] arm64: dts: rockchip: rock-pi-s add more peripherals
+
+This enables the following peripherals:
+* Onboard ethernet support
+* Bluetooth
+* USB 2 port
+* OTG port via type-c connector
+* Hardware watchog
+
+Also add aliases for the mmc devices and the ethernet interface
+
+Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
+Link: https://lore.kernel.org/r/20220614064858.1445817-4-sjoerd@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3308-rock-pi-s.dts    | 52 +++++++++++++++++++
+ 1 file changed, 52 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
+@@ -11,6 +11,12 @@
+ 	model = "Radxa ROCK Pi S";
+ 	compatible = "radxa,rockpis", "rockchip,rk3308";
+
++	aliases {
++		ethernet0 = &gmac;
++		mmc0 = &emmc;
++		mmc1 = &sdmmc;
++	};
++
+ 	chosen {
+ 		stdout-path = "serial0:1500000n8";
+ 	};
+@@ -129,6 +135,15 @@
+ 	status = "okay";
+ };
+
++&gmac {
++	clock_in_out = "output";
++	phy-supply = <&vcc_io>;
++	snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 50000 50000>;
++	status = "okay";
++};
++
+ &i2c1 {
+ 	status = "okay";
+ };
+@@ -192,10 +207,47 @@
+ 	status = "okay";
+ };
+
++&u2phy {
++	status = "okay";
++
++	u2phy_host: host-port {
++		phy-supply = <&vcc5v0_otg>;
++		status = "okay";
++	};
++
++	u2phy_otg: otg-port {
++		phy-supply = <&vcc5v0_otg>;
++		status = "okay";
++	};
++};
++
+ &uart0 {
+ 	status = "okay";
+ };
+
+ &uart4 {
+ 	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8723bs-bt";
++		device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
++		host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
++	};
++};
++
++&usb_host_ehci {
++	status = "okay";
++};
++
++&usb_host_ohci {
++	status = "okay";
++};
++
++&usb20_otg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&wdt {
++	status = "okay";
+ };

target/linux/rockchip/patches-5.19/0027-arm64-dts-rockchip-align-gpio-key-node-names-with-dt.patch

@@ -0,0 +1,369 @@
+From deefbffc188d3b0c9e08fa1ce31bb098839a9995 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Wed, 15 Jun 2022 17:53:19 -0700
+Subject: [PATCH 27/51] arm64: dts: rockchip: align gpio-key node names with
+ dtschema
+
+The node names should be generic and DT schema expects certain pattern
+(e.g. with key/button/switch).
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20220616005333.18491-26-krzysztof.kozlowski@linaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3308-evb.dts   |  2 +-
+ .../boot/dts/rockchip/rk3326-odroid-go2.dts   | 32 +++++++++----------
+ .../boot/dts/rockchip/rk3328-nanopi-r2s.dts   |  2 +-
+ arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi  |  2 +-
+ .../boot/dts/rockchip/rk3368-geekbox.dts      |  2 +-
+ .../dts/rockchip/rk3368-orion-r68-meta.dts    |  2 +-
+ .../boot/dts/rockchip/rk3368-px5-evb.dts      |  2 +-
+ arch/arm64/boot/dts/rockchip/rk3368-r88.dts   |  2 +-
+ .../boot/dts/rockchip/rk3399-firefly.dts      |  2 +-
+ .../dts/rockchip/rk3399-gru-chromebook.dtsi   |  2 +-
+ .../boot/dts/rockchip/rk3399-gru-kevin.dts    |  2 +-
+ .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi |  2 +-
+ .../boot/dts/rockchip/rk3399-khadas-edge.dtsi |  2 +-
+ .../boot/dts/rockchip/rk3399-nanopi-r4s.dts   |  4 +--
+ .../boot/dts/rockchip/rk3399-nanopi4.dtsi     |  2 +-
+ .../boot/dts/rockchip/rk3399-orangepi.dts     |  2 +-
+ .../boot/dts/rockchip/rk3399-pinebook-pro.dts |  4 +--
+ .../boot/dts/rockchip/rk3399-roc-pc.dtsi      |  2 +-
+ .../boot/dts/rockchip/rk3399-rockpro64.dtsi   |  2 +-
+ .../boot/dts/rockchip/rk3399-sapphire.dtsi    |  2 +-
+ .../boot/dts/rockchip/rk3566-pinenote.dtsi    |  2 +-
+ 21 files changed, 38 insertions(+), 38 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3308-evb.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3308-evb.dts
+@@ -75,7 +75,7 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pwr_key>;
+
+-		power {
++		key-power {
+ 			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ 			linux,code = <KEY_POWER>;
+ 			label = "GPIO Key Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
+@@ -71,82 +71,82 @@
+ 		 * |------------------------------------------------|
+ 		 */
+
+-		sw1 {
++		button-sw1 {
+ 			gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
+ 			label = "DPAD-UP";
+ 			linux,code = <BTN_DPAD_UP>;
+ 		};
+-		sw2 {
++		button-sw2 {
+ 			gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
+ 			label = "DPAD-DOWN";
+ 			linux,code = <BTN_DPAD_DOWN>;
+ 		};
+-		sw3 {
++		button-sw3 {
+ 			gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
+ 			label = "DPAD-LEFT";
+ 			linux,code = <BTN_DPAD_LEFT>;
+ 		};
+-		sw4 {
++		button-sw4 {
+ 			gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
+ 			label = "DPAD-RIGHT";
+ 			linux,code = <BTN_DPAD_RIGHT>;
+ 		};
+-		sw5 {
++		button-sw5 {
+ 			gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
+ 			label = "BTN-A";
+ 			linux,code = <BTN_EAST>;
+ 		};
+-		sw6 {
++		button-sw6 {
+ 			gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
+ 			label = "BTN-B";
+ 			linux,code = <BTN_SOUTH>;
+ 		};
+-		sw7 {
++		button-sw7 {
+ 			gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
+ 			label = "BTN-Y";
+ 			linux,code = <BTN_WEST>;
+ 		};
+-		sw8 {
++		button-sw8 {
+ 			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
+ 			label = "BTN-X";
+ 			linux,code = <BTN_NORTH>;
+ 		};
+-		sw9 {
++		button-sw9 {
+ 			gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
+ 			label = "F1";
+ 			linux,code = <BTN_TRIGGER_HAPPY1>;
+ 		};
+-		sw10 {
++		button-sw10 {
+ 			gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
+ 			label = "F2";
+ 			linux,code = <BTN_TRIGGER_HAPPY2>;
+ 		};
+-		sw11 {
++		button-sw11 {
+ 			gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+ 			label = "F3";
+ 			linux,code = <BTN_TRIGGER_HAPPY3>;
+ 		};
+-		sw12 {
++		button-sw12 {
+ 			gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>;
+ 			label = "F4";
+ 			linux,code = <BTN_TRIGGER_HAPPY4>;
+ 		};
+-		sw13 {
++		button-sw13 {
+ 			gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
+ 			label = "F5";
+ 			linux,code = <BTN_TRIGGER_HAPPY5>;
+ 		};
+-		sw14 {
++		button-sw14 {
+ 			gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
+ 			label = "F6";
+ 			linux,code = <BTN_TRIGGER_HAPPY6>;
+ 		};
+-		sw15 {
++		button-sw15 {
+ 			gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
+ 			label = "TOP-LEFT";
+ 			linux,code = <BTN_TL>;
+ 		};
+-		sw16 {
++		button-sw16 {
+ 			gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
+ 			label = "TOP-RIGHT";
+ 			linux,code = <BTN_TR>;
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -34,7 +34,7 @@
+ 		pinctrl-0 = <&reset_button_pin>;
+ 		pinctrl-names = "default";
+
+-		reset {
++		key-reset {
+ 			label = "reset";
+ 			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+ 			linux,code = <KEY_RESTART>;
+--- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
+@@ -76,7 +76,7 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pwr_key>;
+
+-		power {
++		key-power {
+ 			wakeup-source;
+ 			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ 			label = "GPIO Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
+@@ -43,7 +43,7 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pwr_key>;
+
+-		power {
++		key-power {
+ 			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ 			label = "GPIO Power";
+ 			linux,code = <KEY_POWER>;
+--- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
+@@ -44,7 +44,7 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pwr_key>;
+
+-		power {
++		key-power {
+ 			wakeup-source;
+ 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ 			label = "GPIO Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
+@@ -30,7 +30,7 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pwr_key>;
+
+-		power {
++		key-power {
+ 			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ 			label = "GPIO Power";
+ 			linux,code = <KEY_POWER>;
+--- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
+@@ -37,7 +37,7 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pwr_key>;
+
+-		power {
++		key-power {
+ 			wakeup-source;
+ 			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ 			label = "GPIO Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+@@ -87,7 +87,7 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pwrbtn>;
+
+-		power {
++		key-power {
+ 			debounce-interval = <100>;
+ 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ 			label = "GPIO Key Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
+@@ -206,7 +206,7 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&bt_host_wake_l>;
+
+-		wake_on_bt: wake-on-bt {
++		wake_on_bt: key-wake-on-bt {
+ 			label = "Wake-on-Bluetooth";
+ 			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ 			linux,code = <KEY_WAKEUP>;
+--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
+@@ -92,7 +92,7 @@
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>;
+
+-	pen-insert {
++	switch-pen-insert {
+ 		label = "Pen Insert";
+ 		/* Insert = low, eject = high */
+ 		gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
+@@ -183,7 +183,7 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pen_eject_odl>;
+
+-		pen-insert {
++		switch-pen-insert {
+ 			label = "Pen Insert";
+ 			/* Insert = low, eject = high */
+ 			gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+--- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
+@@ -136,7 +136,7 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pwrbtn>;
+
+-		power {
++		key-power {
+ 			debounce-interval = <100>;
+ 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ 			label = "GPIO Key Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+@@ -46,9 +46,9 @@
+ 	gpio-keys {
+ 		pinctrl-0 = <&reset_button_pin>;
+
+-		/delete-node/ power;
++		/delete-node/ key-power;
+
+-		reset {
++		key-reset {
+ 			debounce-interval = <50>;
+ 			gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+ 			label = "reset";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+@@ -111,7 +111,7 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&power_key>;
+
+-		power {
++		key-power {
+ 			debounce-interval = <100>;
+ 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ 			label = "GPIO Key Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
+@@ -78,7 +78,7 @@
+ 		compatible = "gpio-keys";
+ 		autorepeat;
+
+-		power {
++		key-power {
+ 			debounce-interval = <100>;
+ 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ 			label = "GPIO Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+@@ -76,7 +76,7 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&lidbtn_pin>;
+
+-		lid {
++		switch-lid {
+ 			debounce-interval = <20>;
+ 			gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>;
+ 			label = "Lid";
+@@ -92,7 +92,7 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pwrbtn_pin>;
+
+-		power {
++		key-power {
+ 			debounce-interval = <20>;
+ 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ 			label = "Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+@@ -54,7 +54,7 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pwr_key_l>;
+
+-		power {
++		key-power {
+ 			debounce-interval = <100>;
+ 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ 			label = "GPIO Key Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+@@ -42,7 +42,7 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pwrbtn>;
+
+-		power {
++		key-power {
+ 			debounce-interval = <100>;
+ 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ 			label = "GPIO Key Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
+@@ -53,7 +53,7 @@
+ 		compatible = "gpio-keys";
+ 		autorepeat;
+
+-		power {
++		key-power {
+ 			debounce-interval = <100>;
+ 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ 			label = "GPIO Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
+@@ -49,7 +49,7 @@
+ 		pinctrl-0 = <&hall_int_l>;
+ 		pinctrl-names = "default";
+
+-		cover {
++		switch-cover {
+ 			label = "cover";
+ 			gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
+ 			linux,input-type = <EV_SW>;

target/linux/rockchip/patches-5.19/0028-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rk3568-ev.patch

@@ -0,0 +1,40 @@
+From ff2aa1ec6f09917d03959bc2250eccf5f9c24f0c Mon Sep 17 00:00:00 2001
+From: Michael Riesch <michael.riesch@wolfvision.net>
+Date: Wed, 15 Jun 2022 01:03:53 +0200
+Subject: [PATCH 28/51] arm64: dts: rockchip: enable hdmi tx audio on
+ rk3568-evb1-v10
+
+Enable the I2S0 controller and the hdmi-sound node on the Rockchip
+RK3568 EVB1.
+
+Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
+Link: https://lore.kernel.org/r/20220614230354.3756364-1-michael.riesch@wolfvision.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
+@@ -239,6 +239,10 @@
+ 	};
+ };
+
++&hdmi_sound {
++	status = "okay";
++};
++
+ &i2c0 {
+ 	status = "okay";
+
+@@ -496,6 +500,10 @@
+ 	};
+ };
+
++&i2s0_8ch {
++	status = "okay";
++};
++
+ &i2s1_8ch {
+ 	rockchip,trcm-sync-tx-only;
+ 	status = "okay";

target/linux/rockchip/patches-5.19/0029-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rock-3a.patch

@@ -0,0 +1,39 @@
+From f33757d7c1a25febc85546f9a398e23ad449de05 Mon Sep 17 00:00:00 2001
+From: Michael Riesch <michael.riesch@wolfvision.net>
+Date: Wed, 15 Jun 2022 01:03:54 +0200
+Subject: [PATCH 29/51] arm64: dts: rockchip: enable hdmi tx audio on rock-3a
+
+Enable the I2S0 controller and the hdmi-sound node on the Radxa
+ROCK3 Model A.
+
+Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
+Link: https://lore.kernel.org/r/20220614230354.3756364-2-michael.riesch@wolfvision.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -196,6 +196,10 @@
+ 	};
+ };
+
++&hdmi_sound {
++	status = "okay";
++};
++
+ &i2c0 {
+ 	status = "okay";
+
+@@ -436,6 +440,10 @@
+ 	};
+ };
+
++&i2s0_8ch {
++	status = "okay";
++};
++
+ &i2s1_8ch {
+ 	rockchip,trcm-sync-tx-only;
+ 	status = "okay";

target/linux/rockchip/patches-5.19/0030-arm64-dts-rockchip-Add-mt7531-dsa-node-to-BPI-R2-Pro.patch

@@ -0,0 +1,72 @@
+From a502eafcfbed31cb01e71e23553f9348a08c3cfe Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 10 Jun 2022 19:05:41 +0200
+Subject: [PATCH 30/51] arm64: dts: rockchip: Add mt7531 dsa node to BPI-R2-Pro
+ board
+
+Add Device Tree node for mt7531 switch connected to gmac0.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts   | 48 +++++++++++++++++++
+ 1 file changed, 48 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -458,6 +458,54 @@
+ 	status = "okay";
+ };
+
++&mdio0 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	switch@0 {
++		compatible = "mediatek,mt7531";
++		reg = <0>;
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@1 {
++				reg = <1>;
++				label = "lan0";
++			};
++
++			port@2 {
++				reg = <2>;
++				label = "lan1";
++			};
++
++			port@3 {
++				reg = <3>;
++				label = "lan2";
++			};
++
++			port@4 {
++				reg = <4>;
++				label = "lan3";
++			};
++
++			port@5 {
++				reg = <5>;
++				label = "cpu";
++				ethernet = <&gmac0>;
++				phy-mode = "rgmii";
++
++				fixed-link {
++					speed = <1000>;
++					full-duplex;
++					pause;
++				};
++			};
++		};
++	};
++};
++
+ &mdio1 {
+ 	rgmii_phy1: ethernet-phy@0 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";

target/linux/rockchip/patches-5.19/0031-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch

@@ -0,0 +1,87 @@
+From fd0e3d705a8ee61e822c9f4e74c34567a9a31335 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 10 Jun 2022 19:05:37 +0200
+Subject: [PATCH 31/51] net: dsa: mt7530: rework mt7530_hw_vlan_{add,del}
+
+Rework vlan_add/vlan_del functions in preparation for dynamic cpu port.
+
+Currently BIT(MT7530_CPU_PORT) is added to new_members, even though
+mt7530_port_vlan_add() will be called on the CPU port too.
+
+Let DSA core decide when to call port_vlan_add for the CPU port, rather
+than doing it implicitly.
+
+We can do autonomous forwarding in a certain VLAN, but not add br0 to that
+VLAN and avoid flooding the CPU with those packets, if software knows it
+doesn't need to process them.
+
+Suggested-by: Vladimir Oltean <olteanv@gmail.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 30 ++++++++++++------------------
+ 1 file changed, 12 insertions(+), 18 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1527,11 +1527,11 @@ static void
+ mt7530_hw_vlan_add(struct mt7530_priv *priv,
+ 		   struct mt7530_hw_vlan_entry *entry)
+ {
++	struct dsa_port *dp = dsa_to_port(priv->ds, entry->port);
+ 	u8 new_members;
+ 	u32 val;
+
+-	new_members = entry->old_members | BIT(entry->port) |
+-		      BIT(MT7530_CPU_PORT);
++	new_members = entry->old_members | BIT(entry->port);
+
+ 	/* Validate the entry with independent learning, create egress tag per
+ 	 * VLAN and joining the port as one of the port members.
+@@ -1542,22 +1542,20 @@ mt7530_hw_vlan_add(struct mt7530_priv *p
+
+ 	/* Decide whether adding tag or not for those outgoing packets from the
+ 	 * port inside the VLAN.
+-	 */
+-	val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
+-				MT7530_VLAN_EGRESS_TAG;
+-	mt7530_rmw(priv, MT7530_VAWD2,
+-		   ETAG_CTRL_P_MASK(entry->port),
+-		   ETAG_CTRL_P(entry->port, val));
+-
+-	/* CPU port is always taken as a tagged port for serving more than one
++	 * CPU port is always taken as a tagged port for serving more than one
+ 	 * VLANs across and also being applied with egress type stack mode for
+ 	 * that VLAN tags would be appended after hardware special tag used as
+ 	 * DSA tag.
+ 	 */
++	if (dsa_port_is_cpu(dp))
++		val = MT7530_VLAN_EGRESS_STACK;
++	else if (entry->untagged)
++		val = MT7530_VLAN_EGRESS_UNTAG;
++	else
++		val = MT7530_VLAN_EGRESS_TAG;
+ 	mt7530_rmw(priv, MT7530_VAWD2,
+-		   ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
+-		   ETAG_CTRL_P(MT7530_CPU_PORT,
+-			       MT7530_VLAN_EGRESS_STACK));
++		   ETAG_CTRL_P_MASK(entry->port),
++		   ETAG_CTRL_P(entry->port, val));
+ }
+
+ static void
+@@ -1576,11 +1574,7 @@ mt7530_hw_vlan_del(struct mt7530_priv *p
+ 		return;
+ 	}
+
+-	/* If certain member apart from CPU port is still alive in the VLAN,
+-	 * the entry would be kept valid. Otherwise, the entry is got to be
+-	 * disabled.
+-	 */
+-	if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
++	if (new_members) {
+ 		val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
+ 		      VLAN_VALID;
+ 		mt7530_write(priv, MT7530_VAWD1, val);

target/linux/rockchip/patches-5.19/0032-net-dsa-mt7530-rework-mt753-01-_setup.patch

@@ -0,0 +1,75 @@
+From 65046fea942259fb22ae9cdfb86971d8c4e4237b Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 10 Jun 2022 19:05:38 +0200
+Subject: [PATCH 32/51] net: dsa: mt7530: rework mt753[01]_setup
+
+Enumerate available cpu-ports instead of using hardcoded constant.
+
+Suggested-by: Vladimir Oltean <olteanv@gmail.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 25 +++++++++++++++++++++----
+ 1 file changed, 21 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2092,11 +2092,12 @@ static int
+ mt7530_setup(struct dsa_switch *ds)
+ {
+ 	struct mt7530_priv *priv = ds->priv;
++	struct device_node *dn = NULL;
+ 	struct device_node *phy_node;
+ 	struct device_node *mac_np;
+ 	struct mt7530_dummy_poll p;
+ 	phy_interface_t interface;
+-	struct device_node *dn;
++	struct dsa_port *cpu_dp;
+ 	u32 id, val;
+ 	int ret, i;
+
+@@ -2104,7 +2105,19 @@ mt7530_setup(struct dsa_switch *ds)
+ 	 * controller also is the container for two GMACs nodes representing
+ 	 * as two netdev instances.
+ 	 */
+-	dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
++	dsa_switch_for_each_cpu_port(cpu_dp, ds) {
++		dn = cpu_dp->master->dev.of_node->parent;
++		/* It doesn't matter which CPU port is found first,
++		 * their masters should share the same parent OF node
++		 */
++		break;
++	}
++
++	if (!dn) {
++		dev_err(ds->dev, "parent OF node of DSA master not found");
++		return -EINVAL;
++	}
++
+ 	ds->assisted_learning_on_cpu_port = true;
+ 	ds->mtu_enforcement_ingress = true;
+
+@@ -2266,6 +2279,7 @@ mt7531_setup(struct dsa_switch *ds)
+ {
+ 	struct mt7530_priv *priv = ds->priv;
+ 	struct mt7530_dummy_poll p;
++	struct dsa_port *cpu_dp;
+ 	u32 val, id;
+ 	int ret, i;
+
+@@ -2338,8 +2352,11 @@ mt7531_setup(struct dsa_switch *ds)
+ 				 CORE_PLL_GROUP4, val);
+
+ 	/* BPDU to CPU port */
+-	mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
+-		   BIT(MT7530_CPU_PORT));
++	dsa_switch_for_each_cpu_port(cpu_dp, ds) {
++		mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
++			   BIT(cpu_dp->index));
++		break;
++	}
+ 	mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
+ 		   MT753X_BPDU_CPU_ONLY);
+