Adding all rtl files after testing with hardware

rtl/alu.v

@@ -1,3 +1,15 @@
+/**
+ * @file alu.v
+ *
+ * This module implements the simple arithmetics with the values given from control unit.
+ * 
+ * @input in1           Inputs the first sourced value (unsigned only).
+ * @input in2           Inputs the second sourced value (unsigned only).
+ * @input instructions  Inputs the selection line for which process to work.
+ *
+ * @return ALUoutput    Outputs the value calculated.
+*/
+
 
 module alu(
 input [31:0] in1,

rtl/control_unit.v

@@ -1,3 +1,33 @@
+/**
+ * @file control_unit.v
+ * 
+ * This module implements the control unit of a RISC-V processor, handling control signal generation, and data path control. 
+ * The control unit receives input signals such as the opcode, immediate values,
+ * register data, and outputs signals to the ALU, memory, and other components.
+ * 
+ * @param clk          Inputs clock signal.
+ * @param rst          Inputs reset signal.
+ * @param rs1_input    Inputs value from the first source register.
+ * @param rs2_input    Inputs value from the second source register.
+ * @param imm          Immediate value for instructions requiring it.
+ * @param mem_read     Data read from memory.
+ * @param out_signal   Instruction bus from the decoder.
+ * @param opcode       Opcode for instructions from the register file.
+ * @param pc_input     Program counter input address.
+ * @param ALUoutput    Output from the ALU.
+ * 
+ * @return instructions Instruction bus for the ALU.
+ * @return v1           Value going into the ALU from the first source.
+ * @return v2           Value going into the ALU from the second source.
+ * @return mem_write    Data to be written to memory.
+ * @return wr_en        Write enable signal for memory.
+ * @return addr         Address for memory operations.
+ * @return j_signal     Jump signal for control flow instructions.
+ * @return jump         Jump target address.
+ * @return final_output Data to be written to the destination register in the register file.
+ * @return wr_en_rf     Write enable signal for the register file.
+ */
+
 module control_unit(
 	input clk,                                                                                                  //!input clock
 	input rst,                                                                                                  //!reset pin
@@ -40,18 +70,8 @@ end
 always@(*) begin
 	case (opcode)
 		7'b0010011, // I-Type (e.g., ADDI)
-		7'b0000011, // Load Instructions (e.g., LW)
-		7'b1100111: // JALR
+		7'b0000011:
 			Simm <= {{20{imm[31]}}, imm[31:20]};
-
-		7'b0100011: // S-Type (e.g., SW)
-			Simm <= {{20{imm[31]}}, imm[31:25], imm[11:7]};
-
-		7'b1100011: // B-Type (e.g., BEQ)
-			Simm <= {{19{imm[31]}}, imm[31], imm[7], imm[30:25], imm[11:8], 1'b0};
-
-		default:
-			Simm <= 32'b0; // Default case
 	endcase
 	case(opcode)
 		7'b0110011, 7'b0010011 : begin

rtl/data_mem.v

@@ -1,13 +1,26 @@
-
-//! data_mem.v - data memory for single-cycle RISC-V CPU
+/**
+ * @file data_mem.v
+ * 
+ * This module is a memory module with read and write capabilities.
+ *
+ * @param DATA_WIDTH The width of the data bus (default is 32).
+ * @param ADDR_WIDTH The width of the address bus (default is 32).
+ * @param MEM_SIZE   The number of memory locations (default is 64).
+ *
+ * @input clk        Inputs clock signal.
+ * @input wr_en      Write enable signal.
+ * @input wr_addr    Writes Address.
+ * @input wr_data    Writes Data.
+ * 
+ * @return rd_data_mem Output read data.
+*/
 
 module data_mem #(parameter DATA_WIDTH = 32, ADDR_WIDTH = 32, MEM_SIZE = 64) (
     input       clk, wr_en,
     input       [ADDR_WIDTH-1:0] wr_addr, wr_data,
     output      [DATA_WIDTH-1:0] rd_data_mem
 );
 
-//! array of 64 32-bit words or data
 reg [DATA_WIDTH-1:0] data_ram [0:MEM_SIZE-1];
 
 

rtl/decoder.v

@@ -1,3 +1,18 @@
+/**
+ * @file decoder.v
+ * This module works as a decoder of the instruction from the instruction memory.
+ * 
+ * @input instr       32-bit RISC-V Instruction.
+ * 
+ * @return rs1        source register 1 index.
+ * @return rs2        source register 2 index.
+ * @return imm        Immediate value extracted from instruction.
+ * @return rd         Destination register index.
+ * @return rs1_valid  Indicates if rs1 is valid.
+ * @return rs2_valid  Indicates if rs2 is valid.
+ * @return opcode     Operation code from the instruction.
+ * @return out_signal Control signals for various instructions.
+*/
 module decoder(
 
    input [31:0] instr,

rtl/instr_mem.v

@@ -1,5 +1,16 @@
+/**
+ * @file instr_mem.v
+ * This module works as a memory module for instructions to get stored.
+ *
+ * @param DATA_WIDTH Width of the data in bits (default: 32)
+ * @param ADDR_WIDTH Width of the address in bits (default : 32)
+ * @param MEM-SIZE   Number of words in memory (default : 512)
+ *
+ * @input instr_addr Address input for fetching an instruction.
+ * 
+ * @output instr     Output instruction corresponding to the address.
+ */
 
-//! instr_mem.v - instruction memory for single-cycle RISC-V CPU
 
 module instr_mem #(parameter DATA_WIDTH = 32, ADDR_WIDTH = 32, MEM_SIZE = 512) (
     input       [ADDR_WIDTH-1:0] instr_addr,
@@ -8,8 +19,7 @@ module instr_mem #(parameter DATA_WIDTH = 32, ADDR_WIDTH = 32, MEM_SIZE = 512) (
 
 //! array of 64 32-bit words or instructions
 reg [DATA_WIDTH-1:0] instr_ram [0:MEM_SIZE-1];
-parameter HEX_PATH = "/home/shrivishakh/ApexCore/ApexCore.sim/sim_1/behav/xsim";  // Set to local dir
-initial $readmemh({HEX_PATH,"/program_dump.hex"}, instr_ram);
+initial $readmemh({"program_dump.hex"}, instr_ram);
 
 //! word-aligned memory access
 //! combinational read logic

rtl/pc.v

@@ -1,3 +1,18 @@
+/**
+ * @module PC
+ * @brief Program Counter module.
+ * 
+ * This module implements the program counter (PC) for a CPU, updating the PC value
+ * based on clock cycles, reset signal, and jump signal.
+ * 
+ * @input clk      Clock input signal.
+ * @input reset    Reset signal to initialize the program counter.
+ * @input j_signal Jump signal indicating a branch or jump instruction.
+ * @input jump     32-bit jump address to be loaded into the program counter on a jump.
+ * 
+ * @return out_sign Current value of the program counter.
+ */
+
 module PC(
    input clk,
    input reset,

rtl/registerfile.v

@@ -1,4 +1,22 @@
-
+/**
+ * @module registerfile
+ * @brief Register file module for a CPU.
+ * 
+ * This module implements a register file with 32 registers, allowing read and write operations
+ * based on clock cycles, read address signals, and write enable signals.
+ * 
+ * @input clk       Clock input signal.
+ * @input rs1       Register source 1 address (5-bit).
+ * @input rs2       Register source 2 address (5-bit).
+ * @input rs1_valid Indicates if the rs1 register address is valid.
+ * @input rs2_valid Indicates if the rs2 register address is valid.
+ * @input rd        Register destination address (5-bit).
+ * @input wr_en     Write enable signal.
+ * @input rd_value  Value to be written into the register.
+ * 
+ * @return rs1_value Value read from the rs1 register.
+ * @return rs2_value Value read from the rs2 register.
+ */
 module registerfile(
 	input clk,
 	input [4:0]rs1,

rtl/riscv_cpu.v

@@ -1,3 +1,21 @@
+/**
+ * @file riscv_cpu.v
+ * 
+ * This module implements the bare cpu modules, and interconnects various signals
+ * of modules.
+ * 
+ * @input clk         Inputs clock signal.
+ * @input reset       Inputs reset signal.
+ * @input Instr       Inputs Instruction from instruction memory.
+ * @input ReadData    Input Data read from memory.
+ *
+ * @return PC         Output program counter value.
+ * @return MemWrite   Output memory write enable signal.
+ * @return Mem_WrAddr Output memory write enable address.
+ * @return Mem_WrData Output data to be written to memory.
+*/
+
+
 module riscv_cpu (
   input clk, reset,
     output [31:0] PC,
@@ -79,4 +97,4 @@ registerfile registerfile_0(
     .rs2(rs2),
     .rs1_value(source_val1),
     .rs2_value(source_val2));
-endmodule
+endmodule

rtl/seven_seg.v

@@ -1,4 +1,22 @@
-
+/**
+ * @module seven_seg
+ * @brief Seven-segment display driver.
+ * 
+ * This module drives a 7-segment display based on BCD (Binary-Coded Decimal) input.
+ * 
+ * @input clk      Clock input signal.
+ * @input bcd      32-bit BCD input value (used to drive the displays).
+ * @input opcode   7-bit opcode input (for display control).
+ *
+ * @return s1     7-segment display output for the first digit.
+ * @return s2     7-segment display output for the second digit.
+ * @return s3     7-segment display output for the third digit.
+ * @return s4     7-segment display output for the fourth digit.
+ * @return s5     7-segment display output for the fifth digit.
+ * @return s6     7-segment display output for the sixth digit.
+ * @return s7     7-segment display output for the seventh digit.
+ * @return s8     7-segment display output for the eighth digit.
+ */
 
 module seven_seg(
 input clk,

rtl/top.v

@@ -1,13 +1,18 @@
-module top (
-    input clk, reset,
-    //input Ext_MemWrite,
-    //input [31:0] Ext_WriteData, Ext_DataAdr,
-    //output MemWrite,
-    //output [31:0] WriteData, DataAdr, ReadData,
-    //output [31:0] ProgramCounter
-    output led1, led2, led3, led4, led5, led6, led7, led8
-);
+/**
+ * @file top.v
+ * 
+ * This module implements all the modules of the RISC-V processor,
+ * connecting the instruction memory, and data memory with the riscv_cpu module.
+ * Also, it has a simple clock divider logic, to see the output of the cpu logic in 1Hz,
+ * instead of the standard 100MHz generated by the FPGA.
+ *
+ * @input clk_in          Inputs clock signal.
+ * @input reset           Inputs reset signal.
+ * 
+*/
 
+module top (
+    input clk, reset);
 //! wire lines from other modules
 wire [7:0] led;
 wire [31:0] PC;
@@ -22,12 +27,4 @@ riscv_cpu rvsingle (clk, reset, PC, Instr, MemWrite_rv32, DataAdr_rv32, WriteDat
 instr_mem imem (PC, Instr);
 data_mem dmem (clk, MemWrite_rv32, DataAdr_rv32, WriteData_rv32, ReadData);
 
-//! output assignments
-//assign MemWrite = (Ext_MemWrite && reset) ? 1 : MemWrite_rv32;
-//assign WriteData = (Ext_MemWrite && reset) ? Ext_WriteData : WriteData_rv32;
-//assign DataAdr = (reset) ? Ext_DataAdr : DataAdr_rv32;
-assign led [7:0] = WriteData_rv32 [7:0];
-led led_0 (clk, led, led1, led2, led3, led4, led5 ,led6, led7, led8);
-
 endmodule
-