This is originally a project for the course CS202 by SUSTech, by Zephyrus Zhang, David Li and Marsy. But since this is perhaps the most detailed documentation and has the best illustrations around, not just giving in-depth explanations about complicated pipelined CPU, but also for 4 by 4 keypad, VGA display, and seven segment tube display.
The CPU can perform IO interrupts and has a memory mapped IO. The module diagram is given below (with some signals not drawn). More graphs, additional programs, IP core, script and detailed explanation of all the modules are provided [here].
