Insert delay after release power-down SPI flash command

[joshtyler]

SPI flash chips which support entering the power-down state require a delay after the release from power down command (ABh) before they are operational. This PR implements that delay for picosoc, where previously no delay was present. Without this PR I found that my board was able to boot reliably with a 10 MHz system clock, but not 25 MHz, despite being out of spec at both rates.

I looked at a few different SPI flash chips to find a reasonable delay:

• The chip I am using on my board (W25Q128JVS) requires 3us
• The chip used in ICEBreaker (W25Q128JVSIM) requires 3us
• A Micron chip that was is readily available ( MT25QL128ABA1ESE-0SIT) requires 30us
• The chip fitted to the Lattice HX8K breakout board (N25Q032A13ESC40F) doesn't support the power-down mode.

To try and account for all reasonable delays without being excessive, I have chosen 2^12 cycles. It meets the Micron required delay at 100MHz, whilst being less than 0.5ms at 10MHz. I'm happy to change this to be a parameter if you would prefer.

N.B. I have only tested this in simulation, and with my custom PCB using the default single bit wide I/O mode. I haven't tested with an ICEBreaker, or the Lattice dev board.