UART Baud rate error

[RobPearce]

This could be considered a documentation error.
The Baud rate calculation is wrong as stated. I was trying to reuse a derivative of the module and testing with 1MBaud off a 12MHz clock (divider of 12) and found that the bits were 14 clocks long.
The "cfg_divider" is specified in the README as the simple ratio of clock to Baud.
At line 90 of simpleuart.v (also 84, 97, 130) the bit timing counter is tested for being strictly greater than this and, if so, cleared to zero onthenextclock*. Thus with a divider of 12, the counter cycles through from 0 to 13, giving a total of 14 counts.
The fix, I would suggest, is in two parts. First, change all of those ">" tests to ">=". Second, specify the cfg_divider as (clk/Baud)-1 (which is very common in hardware UART Baud generator registers).

[ghost]

Been playing with a testbench for simpleuart, and can confirm, see screenshot for simplest example with div = 1 (right after reset):