make pc point to EXC_BRANCH inst

Xinlong-Wu · Dec 25, 2023 · ef63c61 · ef63c61
1 parent f377e84
commit ef63c61
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Showing 3 changed files with 16 additions and 15 deletions.
diff --git a/src/mono/mono/mini/cpu-riscv64.mdesc b/src/mono/mono/mini/cpu-riscv64.mdesc
@@ -235,11 +235,11 @@ riscv_bge: src1:i src2:i len:8
 riscv_bgeu: src1:i src2:i len:8
 riscv_blt: src1:i src2:i len:8
 riscv_bltu: src1:i src2:i len:8
-riscv_exc_beq: src1:i src2:i len:12
-riscv_exc_bne: src1:i src2:i len:12
-riscv_exc_bgeu: src1:i src2:i len:12
-riscv_exc_blt: src1:i src2:i len:12
-riscv_exc_bltu: src1:i src2:i len:12
+riscv_exc_beq: src1:i src2:i len:16
+riscv_exc_bne: src1:i src2:i len:16
+riscv_exc_bgeu: src1:i src2:i len:16
+riscv_exc_blt: src1:i src2:i len:16
+riscv_exc_bltu: src1:i src2:i len:16
 riscv_slt: dest:i src1:i src2:i len:4
 riscv_sltu: dest:i src1:i src2:i len:4
 riscv_slti: dest:i src1:i len:4

diff --git a/src/mono/mono/mini/exceptions-riscv.c b/src/mono/mono/mini/exceptions-riscv.c
@@ -83,7 +83,7 @@ mono_riscv_throw_exception (gpointer arg, host_mgreg_t pc, host_mgreg_t *int_reg
 	}
 
 	/* Adjust pc so it points into the call instruction */
-	pc -= 4;
+	pc--;
 
 	/* Initialize a ctx based on the arguments */
 	memset (&ctx, 0, sizeof (MonoContext));

diff --git a/src/mono/mono/mini/mini-riscv.c b/src/mono/mono/mini/mini-riscv.c
@@ -3662,9 +3662,9 @@ mono_riscv_emit_load_regarray (guint8 *code, guint64 regs, int basereg, int offs
 	g_assert (basereg != RISCV_SP);
 
 	if (!RISCV_VALID_S_IMM (offset)) {
-		code = mono_riscv_emit_imm (code, RISCV_T6, offset);
-		riscv_add (code, RISCV_T6, basereg, RISCV_T6);
-		basereg = RISCV_T6;
+		code = mono_riscv_emit_imm (code, RISCV_T0, offset);
+		riscv_add (code, RISCV_T0, basereg, RISCV_T0);
+		basereg = RISCV_T0;
 		offset = 0;
 	}
 
@@ -3694,9 +3694,9 @@ mono_riscv_emit_store_regarray (guint8 *code, guint64 regs, int basereg, int off
 	g_assert (basereg != RISCV_SP);
 
 	if (!RISCV_VALID_S_IMM (offset)) {
-		code = mono_riscv_emit_imm (code, RISCV_T6, offset);
-		riscv_add (code, RISCV_T6, basereg, RISCV_T6);
-		basereg = RISCV_T6;
+		code = mono_riscv_emit_imm (code, RISCV_T0, offset);
+		riscv_add (code, RISCV_T0, basereg, RISCV_T0);
+		basereg = RISCV_T0;
 		offset = 0;
 	}
 
@@ -3725,9 +3725,9 @@ mono_riscv_emit_load_stack (guint8 *code, guint64 regs, int basereg, int offset,
 	g_assert (basereg != RISCV_SP);
 
 	if (!RISCV_VALID_S_IMM (offset)) {
-		code = mono_riscv_emit_imm (code, RISCV_T6, offset);
-		riscv_add (code, RISCV_T6, basereg, RISCV_T6);
-		basereg = RISCV_T6;
+		code = mono_riscv_emit_imm (code, RISCV_T0, offset);
+		riscv_add (code, RISCV_T0, basereg, RISCV_T0);
+		basereg = RISCV_T0;
 		offset = 0;
 	}
 
@@ -3994,6 +3994,7 @@ static guint8 *
 mono_riscv_emit_branch_exc (MonoCompile *cfg, guint8 *code, int opcode, int sreg1, int sreg2, const char *exc_name)
 {
 	riscv_auipc (code, MONO_ARCH_EXC_ADDR_REG, 0);
+	riscv_addi (code, MONO_ARCH_EXC_ADDR_REG, MONO_ARCH_EXC_ADDR_REG,8);
 	switch (opcode) {
 	case OP_RISCV_EXC_BEQ:
 		riscv_bne (code, sreg1, sreg2, 8);