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Failed to find an OpenCL platform YOLOv2 Demo on AWS #20

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esberglu opened this issue Jul 19, 2018 · 6 comments
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Failed to find an OpenCL platform YOLOv2 Demo on AWS #20

esberglu opened this issue Jul 19, 2018 · 6 comments

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@esberglu
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I'm getting the following error running the yolo demo app on AWS with "./run.sh aws e2e". The compile and quantization steps appear to be completing successfully, xyolo is failing.

INFO: Entering XYOLO WITH
Finished batch 1
[XBLAS] # kernels: 1
[0]user:0xf010:0x1d51:[???:??:0]
xclProbe found 1 FPGA slots with xocl driver running
WARNING: AwsXcl - Cannot open userPF: /dev/dri/renderD0
WARNING: AwsXcl isGood: invalid user handle.
WARNING: xclOpen Handle check failed
[0]user:0xf010:0x1d51:[???:??:0]
device[0].user_instance : 0
WARNING: AwsXcl - Cannot open userPF: /dev/dri/renderD0
WARNING: AwsXcl isGood: invalid user handle.
ERROR: xclOpen Handle check failed
ERROR: Failed to find an OpenCL platform

@wilderfield
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wilderfield commented Jul 19, 2018 via email

@esberglu
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Thanks again, I was able to complete the yolo demo with this fix and #19, with some caveats.

The sdaccel_setup.sh script requires that you are using the 2017.4 version on Xilinx SDx [1] [2]. For now I just changed those to checks to 2017.1, which is the version found on the AWS instance.

The Makefile then was unable to find the libstdc++.so file in the expected location [3]. For now I just searched the filesystem for a libstdc++.so and changed the path in the install command to point that location. After that the sdaccel_setup.sh ran to completion and I was able to finish the yolo demo. However I am not confident that either of those solutions is the "correct" way to be doing things. Perhaps you are aware of a better solution.

[1] https://github.com/aws/aws-fpga/blob/2fdf23ffad944cb94f98d09eed0f34c220c522fe/sdaccel_setup.sh#L160
[2] https://github.com/aws/aws-fpga/blob/2fdf23ffad944cb94f98d09eed0f34c220c522fe/SDAccel/Makefile#L39
[3] https://github.com/aws/aws-fpga/blob/2fdf23ffad944cb94f98d09eed0f34c220c522fe/SDAccel/Makefile#L81

@wilderfield
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wilderfield commented Jul 20, 2018 via email

@esberglu
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Ah I was using the Xilinx ML Suite AMI, not the FPGA Developer AMI. Sounds like that's my problem. I'll give it a try with FPGA Developer AMI.

@kamranjk
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Hi Eric,

sorry about that. We are in the process of updating the AMI to support the latest ML Suite. Should be ready shortly, but as you can start with the FPGA Dev AMI today.

Thanks,
kamran

@esberglu
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It worked with modifications and no issues with the FPGA Dev AMI. Thanks!

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