PFM/D/SOM, VCK190 and DFX: add iteration guideline, IP address modification reference and device tree know-how cross link

Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/Iteration_guideline.md

@@ -0,0 +1,37 @@
+<table class="sphinxhide" width="100%">
+ <tr width="100%">
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Vitis™ Platform Creation Tutorials</h1>
+    <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
+    </td>
+ </tr>
+</table>
+
+## Iteration Guidelines
+
+When using Vitis flow to create platform and develop acceleration applications, iteration could be divided into three cases: hardware updates, software update and application. Iteration steps should obey from the following steps.
+
+1. Hardware updates
+
+    - Reexport the **XSA** file if you update the Hardware design in [Step1](step1.md)
+    - Update the Hardware specification in [Step2](step2.md). Right click the platform and select **Update Hardware Specification**, then choose the updated **XSA** file and rebuild the platform.
+
+    ![image](./images/update_hw.PNG)
+
+    - Clean the Application and rebuild the Application in [Step3](step3.md)
+
+2. Software component updates
+
+    - Copy the software component to boot or sd_dir directory if you update the boot components in [step2](step2.md). Then clean the platform and rebuild the platform. For example, if DTB is updated, please copy new DTB to boot directory. Then clean the platform and rebuild it again. You would get updated platform.
+    - Clean the Application and rebuild the Application in [Step3](step3.md)
+
+3. Application updates
+
+    - If user update the host code, they just need to clean the host first and then rebuild the host. After copying the host ELF to the fat partition of the sd card.
+    - If user update the Kernel code, they just need to clean the kernel and hardware link first and then rebuild the kernel and hardware link. After coping the XCLBIN file to the fat partition of the sd card.
+
+When using Vitis export to Vivado flow to develop acceleration application, please follow [Vitis Export to Vivdao](../../Feature_Tutorials/03_Vitis_Export_To_Vivado) to do iteration.
+
+
+<p class="sphinxhide" align="center"><sub>Copyright © 2020–2023 Advanced Micro Devices, Inc</sub></p>
+
+<p class="sphinxhide" align="center"><sup><a href="https://www.amd.com/en/corporate/copyright">Terms and Conditions</a></sup></p>

Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md

@@ -65,6 +65,8 @@ The platform creation steps are introduced in the following pages. Each page des
 - [Step 1: Create the Vivado Hardware Design and Generate XSA](./step1.md)
 - [Step 2: Create the Vitis Platform](./step2.md)
 - [Step 3: Test the Platform](./step3.md)
+- [Iteration Guidelines](./Iteration_guideline.md)
+
 
 ***Start from [Step 1: Vivado Design](./step1.md).***
 

Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step1.md

@@ -220,6 +220,25 @@ For simple designs, interrupt signals can be sourced by processor's **pl_ps_irq*
 
       ![Platform Setup - AXI Ports](images/platform_setup_interfaces.png)
 
+### Modify the IP address in address editor (Optional)
+
+   >Note: This step is not mandatory for platform creation. Please refer to it according to your requirement.
+
+   If users need to modify the IP address please go through following steps.
+   1. Check the location address space of your IP 
+   2. Go to address editor by clicking **Window**-> **Address editor** to open it.
+
+   Next, we will use the example of modifying the interrupt controller IP address to illustrate how to modify the IP address in the address editor.
+
+   - As the interrupt controller is connected with **M_AXI_HPM0_LPD** domain, we need check LPD domain supported address space. Please check the [ZYNQMP Technical Reference Manual](https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/PL-AXI-Interface). You could find following address range. That means the IP connected to LPD domain could be placed in 0x8000_0000-0x9FFF_FFFF address space. But conflict is not allowed.
+
+      ![Platform Setup - AXI Ports](images/LPD.PNG)
+
+   - Go to address editor, modify the interrupt controller IP base address according to your requirement.
+
+      ![Platform Setup - AXI Ports](images/address.PNG)
+
+   >Note: The modified base address should be in the LPD address space and the high address should also be in the LPD address space.
 ### Export Hardware XSA
 
 1. Validate the block design

Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step2.md

@@ -148,6 +148,8 @@ If you need to do system customization, take the following steps as reference. F
 
    > **NOTE:** Createdts is a command executing in XSCT console to generate device files. This command needs several inputs to generate the device tree files. Regarding the meaning of every option, you can execute a help command to check the details. Besides XSCT is a Console tool of Vitis. You can start it by typing `xsct` in Linux terminal to start it. Or, you can select menu **Xilinx > XSCT Console** to start the XSCT tool after you launch Vitis.
 
+   > **NOTE**: Device tree knowledge is a common know-how. Please refer to [AMD Device tree WIKI page](https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/862421121/Device+Trees) or [Device Tree WIKI page](https://en.wikipedia.org/wiki/Devicetree#Linux) for more information if you are not familiar with it.
+
    Execute the following command to exit XSCT console.
 
    ```bash

Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step3.md

@@ -237,6 +237,10 @@ The command line flow has slight differences comparing to Vitis IDE flow.
 
 - The vector addition application is called `vadd` and `binary_container_1.xclbin` in Vitis IDE flow. The generated files in command line flow are called `simple_vadd` and `krnl_vadd.xclbin`.
 
+### Next Steps
+
+If user need to do iteration for your project, you could go through the [Iteration Guidelines](./Iteration_guideline.md) to do iterations.
+
 <p class="sphinxhide" align="center"><sub>Copyright © 2020–2023 Advanced Micro Devices, Inc</sub></p>
 
 <p class="sphinxhide" align="center"><sup><a href="https://www.amd.com/en/corporate/copyright">Terms and Conditions</a></sup></p>

Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/Iteration_guideline.md

@@ -0,0 +1,37 @@
+<table class="sphinxhide" width="100%">
+ <tr width="100%">
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Vitis™ Platform Creation Tutorials</h1>
+    <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
+    </td>
+ </tr>
+</table>
+
+## Iteration Guidelines
+
+When using Vitis flow to create platform and develop acceleration applications, iteration could be divided into three cases: hardware updates, software update and application. Iteration steps should obey from the following steps.
+
+1. Hardware updates
+
+    - Reexport the **XSA** file if you update the Hardware design in [Step1](step1.md)
+    - Update the Hardware specification in [Step2](step2.md). Right click the platform and select **Update Hardware Specification**, then choose the updated **XSA** file and rebuild the platform.
+
+    ![image](./images/update_hw.PNG)
+
+    - Clean the Application and rebuild the Application in [Step3](step3.md)
+
+2. Software component updates
+
+    - Copy the software component to boot or sd_dir directory if you update the boot components in [step2](step2.md). Then clean the platform and rebuild the platform. For example, if DTB is updated, please copy new DTB to boot directory. Then clean the platform and rebuild it again. You would get updated platform.
+    - Clean the Application and rebuild the Application in [Step3](step3.md)
+
+3. Application updates
+
+    - If user update the host code, they just need to clean the host first and then rebuild the host. After copying the host ELF to the fat partition of the sd card.
+    - If user update the Kernel code, they just need to clean the kernel and hardware link first and then rebuild the kernel and hardware link. After coping the XCLBIN file to the fat partition of the sd card.
+
+When using Vitis export to Vivado flow to develop acceleration application, please follow [Vitis Export to Vivdao](../../Feature_Tutorials/03_Vitis_Export_To_Vivado) to do iteration.
+
+
+<p class="sphinxhide" align="center"><sub>Copyright © 2020–2023 Advanced Micro Devices, Inc</sub></p>
+
+<p class="sphinxhide" align="center"><sup><a href="https://www.amd.com/en/corporate/copyright">Terms and Conditions</a></sup></p>

Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/README.md

@@ -41,6 +41,7 @@ Navigate through these steps with the following table of contents links.
 - [Step 1: Create a Hardware Design](./step1.md)
 - [Step 2: Create a Vitis Platform](./step2.md)
 - [Step 3: Run Applications on the Vitis Platform](./step3.md)
+- [Iteration Guidelines](./Iteration_guideline.md)
 - [Frequently Asked Questions](faq.md)
 
 ## Reference

Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/step1.md

@@ -147,6 +147,25 @@ In this step, you will create a hardware design using the AMD Versal™ Adaptive
 
 Now you have completed the hardware design. In the coming steps, you will review the platform-related property settings.
 
+### Modify the IP address in address editor (Optional)
+
+   >Note: This step is not mandatory for platform creation. Please refer to it according to your requirement.
+
+   If users need to modify the IP address please go through following steps.
+   1. Check the location address space of your IP 
+   2. Go to address editor by clicking **Window**-> **Address editor** to open it.
+
+   Next, we will use the example of modifying the interrupt controller IP address to illustrate how to modify the IP address in the address editor.
+
+   - As the interrupt controller is connected with **M_AXI_FPD** domain, we need check FPD domain supported address space. Please check the [Versal Technical Reference Manual](https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/High-level-Address-Map). You could find following address range. That means the IP connected to FPD domain could be placed in 0xA400_0000-0xAFFF_FFFF or 0xB000_0000-0xBFFF_FFFF address space. But conflict is not allowed.
+
+      ![Platform Setup - AXI Ports](images/step1/FPD.PNG)
+
+   - Go to address editor, modify the interrupt controller IP base address according to your requirement. Following is just an example.
+
+      ![Platform Setup - AXI Ports](images/step1/versal_address.PNG)
+
+   >Note: The modified base address should be in the LPD address space and the high address should also be in the LPD address space.
 ### Review the Versal Extensible Platform Example Part_base Platform Setup
 
 1. (Optional) Export block diagram Tcl to cross check the Tcl commands, or recreate design in the future.

Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/step2.md

@@ -108,6 +108,9 @@ Utilize XSCT tool to execute one command to generate device tree files:
 
    > **NOTE:** `createdts` is a command executing in XSCT console to generate device files. This command needs several inputs to generate the device tree files. Regarding the meaning of every option, you can execute the `help` command to check the details. Besides XSCT is a Console tool of Vitis. You can start it by typing `xsct` in Linux terminal to start it. Or you can select menu **Xilinx > XSCT Console** to start the XSCT tool after you launch Vitis.
 
+   > **NOTE**: Device tree knowledge is a common know-how. Please refer to [AMD Device tree WIKI page](https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/862421121/Device+Trees) or [Device Tree WIKI page](https://en.wikipedia.org/wiki/Devicetree#Linux) for more information if you are not familiar with it.
+
+
    Execute the following command to exit XSCT console.
 
    ```bash

Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/step3.md

@@ -354,6 +354,11 @@ Vitis runs PS emulation in QEMU, PL and AIE emulation in XSIM. They can communic
 
 Congratulations now you've created a custom platform that PL acceleration kernel and AIE applications can work on it.
 
+### Next Steps
+
+If user need to do iteration for your project, you could go through the [Iteration Guidelines](./Iteration_guideline.md) to do iterations.
+
+
 [In next chapter](./faq.md), we'll list some frequently encountered problems and frequently asked questions. Please take a look if you'd like to understand more of platform creation.
 
 

Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/Iteration_guideline.md

@@ -0,0 +1,37 @@
+<table class="sphinxhide" width="100%">
+ <tr width="100%">
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Vitis™ Platform Creation Tutorials</h1>
+    <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
+    </td>
+ </tr>
+</table>
+
+## Iteration Guidelines
+
+When using Vitis flow to create platform and develop acceleration applications, iteration could be divided into three cases: hardware updates, software update and application. Iteration steps should obey from the following steps.
+
+1. Hardware updates
+
+    - Reexport the **XSA** file if you update the Hardware design in [Step1](step1.md)
+    - Update the Hardware specification in [Step2](step2.md). Right click the platform and select **Update Hardware Specification**, then choose the updated **XSA** file and rebuild the platform.
+
+    ![image](./images/update_hw.PNG)
+
+    - Clean the Application and rebuild the Application in [Step3](step3.md)
+
+2. Software component updates
+
+    - Copy the software component to boot or sd_dir directory if you update the boot components in [step2](step2.md). Then clean the platform and rebuild the platform. For example, if DTB is updated, please copy new DTB to boot directory. Then clean the platform and rebuild it again. You would get updated platform.
+    - Clean the Application and rebuild the Application in [Step3](step3.md)
+
+3. Application updates
+
+    - If user update the host code, they just need to clean the host first and then rebuild the host. After copying the host ELF to the fat partition of the sd card.
+    - If user update the Kernel code, they just need to clean the kernel and hardware link first and then rebuild the kernel and hardware link. After coping the XCLBIN file to the fat partition of the sd card.
+
+When using Vitis export to Vivado flow to develop acceleration application, please follow [Vitis Export to Vivdao](../../Feature_Tutorials/03_Vitis_Export_To_Vivado) to do iteration.
+
+
+<p class="sphinxhide" align="center"><sub>Copyright © 2020–2023 Advanced Micro Devices, Inc</sub></p>
+
+<p class="sphinxhide" align="center"><sup><a href="https://www.amd.com/en/corporate/copyright">Terms and Conditions</a></sup></p>

Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/README.md

@@ -35,6 +35,7 @@ Navigate through this tutorial using the following table of contents links.
 - [Step 1: Hardware Settings for Vitis Platform](./step1.md)
 - [Step 2: Create the Software Components and Generate Platform](./step2.md)
 - [Step 3: Test the Platform](./step3.md)
+- [Iteration Guidelines](./Iteration_guideline.md)
 - [Frequently Asked Questions](faq.md)
 
 ## Requirements and Assumptions

Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step1.md

@@ -86,6 +86,25 @@ At this stage, the Vivado block automation has already created a top block desig
 
 The next sections explain the sub-module in this CED DFX platform. The submodule design methodology is applied to all the DFX design.
 
+### Modify the IP address in address editor (Optional)
+
+   >Note: This step is not mandatory for platform creation. Please refer to it according to your requirement.
+
+   If users need to modify the IP address please go through following steps.
+   1. Check the location address space of your IP 
+   2. Go to address editor by clicking **Window**-> **Address editor** to open it.
+
+   Next, we will use the example of modifying the interrupt controller IP address to illustrate how to modify the IP address in the address editor.
+
+   - As the interrupt controller is connected with **M_AXI_FPD** domain, we need check FPD domain supported address space. Please check the [Versal Technical Reference Manual](https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/High-level-Address-Map). You could find following address range. That means the IP connected to FPD domain could be placed in 0xA400_0000-0xAFFF_FFFF or 0xB000_0000-0xBFFF_FFFF address space. But conflict is not allowed.
+
+      ![Platform Setup - AXI Ports](images/step1/FPD.PNG)
+
+   - Go to address editor, modify the interrupt controller IP base address according to your requirement. Following is just an example.
+
+      ![Platform Setup - AXI Ports](images/step1/versal_address.PNG)
+
+   >Note: The modified base address should be in the LPD address space and the high address should also be in the LPD address space.
 ### DFX Platform Design Submodule Explanation
 
 The following sections provide the platform hardware submodule explanation with diagrams. In the diagrams, the Vitis region is the dynamic area (RP). Blocks outside of the Vitis Region are in the static region. They will be loaded at boot time and won't be reconfigured.

Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step2.md

@@ -77,6 +77,8 @@ createdts -hw <static XSA> \
 
 The generated device tree files are located in ``build/vck190_custom_dt/psv_cortexa72_0/device_tree_domain/bsp`` path. You can find the ``system.dtb`` file in ``step2_sw/build/vck190_custom_dt/psv_cortexa72_0/device_tree_domain/bsp/`` directory.
 
+> **NOTE**: Device tree knowledge is a common know-how. Please refer to [AMD Device tree WIKI page](https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/862421121/Device+Trees) or [Device Tree WIKI page](https://en.wikipedia.org/wiki/Devicetree#Linux) for more information if you are not familiar with it.
+
 ### Creating the Vitis Platform
 
 The Vitis platform creation workflow for DFX platforms is almost identical to the flat platform with the following exceptions

Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step3.md

@@ -497,6 +497,10 @@ To verify the platform functionality, you will create a project with an AI Engin
 
 Congratulations now you have created a custom platform that the PL acceleration kernel and AI Engine applications can work on it.
 
+### Next Steps
+
+If user need to do iteration for your project, you could go through the [Iteration Guidelines](./Iteration_guideline.md) to do iterations.
+
 ## What's Next
 
 [The next chapter](./faq.md) will list some frequently encountered problems and frequently asked questions.