<01-aie_lenet_tutorial>: <Can't run the project on the VCK190 board> #376
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CRTejaswi
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Oct 3, 2023
6f98ae9 Merge pull request Xilinx#420 from amalv/vmc_merge e182b6a Merge pull request Xilinx#419 from RepoOps/remove_HOST_ARCH_docs_2 8126d7a Merge pull request Xilinx#414 from mlechtan/next 39daecc Merge branch 'next' into next 9964e4a Merge pull request Xilinx#422 from mlechtan/description_fix 15a7794 Updating description.json per latest spec b5f1fa7 Merge branch 'next' into next a017126 Merge pull request Xilinx#415 from uvimalku/update_datamover_descriptionjson dd02ba3 removing vmc_ files from L2/meta as they are in meta/vmc 95fabaf Merging VMC related changes to metadata, verify and merge to main c0766c8 remove HOST_ARCH from docs 4410460 Merge pull request Xilinx#417 from mlechtan/description_fix 71e9f77 Merge pull request Xilinx#418 from mlechtan/config_translation_fix 625fb93 script changes to matmul shuffle 629ed34 Updating sourced script's path 9ce8267 Merge pull request Xilinx#416 from mlechtan/fir_int_hb_fix 6842813 Updating description.json flags per latest spec. c1a83e9 Regenerate FIR Int HB Makefile d72934a Extending stacksize allocation. bd5b6a1 Updated access funtion call. 71d7c63 FIR Interpolate HB access function update. a156d41 Reverting FIR Resampler SSR template addition. 04d6822 update description.json to include host source file paths c9de463 Merge branch 'FaaSApps:next' into next f3d6edc Merge pull request Xilinx#413 from mlechtan/gui_update c9ea982 Tidy up. Making helper functions private. 436a841 Regenerate aie Makefiles 6432f2f Extending stacksize allocation. 9e4537b Adding SSR testbench structure. 7da2e7a Updated access funtion call. 63a8980 FIR Interpolate HB access function update. c851283 Adding Resampler's SSR params. 33a8ea5 Tidy up. 4e0dc4f Update gui parameter values 7e6c42e Merge pull request Xilinx#412 from liyuanz/a+m 4acc5dc Merge pull request Xilinx#410 from liyuanz/next ac82961 Merge branch 'next' into a+m 4924b5b add memory 9a420a4 Merge pull request Xilinx#406 from justusr/next 425b012 update mk 29ff113 Look fr 'L2' in pwd instead of 'xf_dsp' in common config json to ensure that it runs for different names of the xfdsp repo. This is particularly relevant beacause jenkins uses a different name. 27d4bc9 Merge branch 'FaaSApps:next' into next 663ae68 Merge pull request Xilinx#409 from mlechtan/next a94b2e1 Adding condition to call to connect<> for coeff parameter bfb8c3d Merge pull request Xilinx#407 from mlechtan/next 30ad782 Merge pull request Xilinx#408 from liyuanz/next 9b5ab8a add time 0d277fb Update SSR testcase to single parallel polyphase cacc399 Adding a testcase for FIR Interpolate Asym SSR RTP Coeff Update da6a607 Adding xRouter option to use DMA FIFOs in free banks on ff14c6d FIR Interpolate Asym RTP SSR Coeff Update. fad9aed Merge pull request #1 from justusr/debug_practise 97b98b9 Merge branch 'debug_practise' of https://gitenterprise.xilinx.com/justusr/xf_dsp into debug_practise 0d6bc0a Split makefile-config parameter translation into two files so it's easier to read for the test suite in dsplib_internal_scripts. c31c9cb Merge pull request Xilinx#402 from mlechtan/next 3eaf74c Merge pull request Xilinx#403 from mlechtan/fir_dec_sym_rtp d790b40 Merge pull request Xilinx#405 from liyuanz/next 346dc54 add time for time limit case 61b3903 add time for time limit case 3257dcf Merge pull request Xilinx#404 from liyuanz/add_m 4f6a67a add mem e15667d Removing constraint around SSR configs d02eb2a Adding xRouter option to use DMA FIFOs in free banks on 312206c Adding SSR RTP coeff reload testcases. f74bc85 FIR Dec Sym RTP Coeff update for SSR configs. edb7877 Fix for m_rawTaps array length size. 524e904 Testcase config tweak to fix stacksize calculation dd5e0cb Adding xRouter option to use DMA FIFOs in free banks only. 960db32 Merge pull request Xilinx#400 from mlechtan/next c400eeb Accomodating Dec HB SSR RTP Coeff update with FIR LEN % SSR != 0. 4064797 Merge pull request Xilinx#396 from yuanqian/update_next_doc 813b206 addd .gitignore 780a653 Reverting convert_sym_taps_to_asym changes. 091d96f Adjusting min cascade call for single rate FIRs 6df0674 Tidy up param struct names 986e578 Adding TP_COEFF_PHASES_LEN driver for SR FIR graphs. e6c2e7e Fix for SSR RTP Coeff Reload with Cascaded FIRs. 2574bf1 FIR Decimate Asym SSR RTP Coeff Reload. 1afcc51 Merge pull request Xilinx#401 from liyuanz/add_mem_2 024c0fb add time a5bf9c7 Adding reworked SR Asym access functions. d8edceb add time 558eefc add mem 5aad20b Fixing testcase definition 175f520 Tidy up. Removing excessive prints. a11d1d5 Adding testcase for RTP Coeff Reload on SSR. 496a6a3 Adding support for RTP Coeff Reload for SSR cases to FIR Dec HB 3c18de5 Merge branch 'next' of https://gitenterprise.xilinx.com/mlechtan/xf_dsp into next 358ee0b Adding extra template parameters for RTP Coeff update or SSR. d573717 HB Int: removing __restrict from CT coeff pointer. 9bd68ef Merge branch 'FaaSApps:next' into next b47bb90 Merge pull request Xilinx#399 from uvimalku/update-metadata-maxtaps-window 663e319 correct maxTapsPerKernel 3c2c2cc update 147a5b4 Merge branch 'FaaSApps:next' into next 134a5f7 Adding testcase for RTP Coeff Reload on SSR. 7f78f90 Adding support for RTP Coeff Reload for SSR cases to FIR Int HB dc063e4 Adding case for RTP Coeff Reload on SSR design. 42b4aa9 Adding support for RTP Coeff Reload for SSR cases 261d6ae Merge pull request Xilinx#398 from liyuanz/add_mem f5a2e44 add memory cccd472 Merge pull request Xilinx#397 from mlechtan/next f4208cb Fir resampler ref input file name defined 7404c13 Removing redundant function calls 5d1c830 Fixing removed/changed UUT_PARA_POLY params 26aafa1 Reconfiguring FIRs reference input/output file names a5f48fc Updating Makefiles for AIE cases a245cbb FiAdding REF_OUTPUT_WINDOW_VSIZE to FIRs 346390e Adding Ref models output file mods bfcf3f0 Removing redundant kernel access functions. 37b92b6 Merge branch 'next' of https://gitenterprise.xilinx.com/mlechtan/xf_dsp into next 4768fdb Tidy up. Move FIRs common_traits features to graphs. c0b7cbe Merge branch 'FaaSApps:next' into next f142c50 Tidy up in preparation for SSR Coeff Reload 6ef1412 Tidy up reference models for Asym FIRs wrt Header based Coeff Reload. b5a29c7 Merge pull request Xilinx#395 from mlechtan/next 1a4d8d9 Fixing Coeff Reload Header mode calc. cb48c89 Merge pull request Xilinx#394 from uvimalku/decimate_sym_ssr_metadata_updates fdfdce0 update 238cf7b Relaxing Metadata constraints wrt Coeff reload on SSR 64e2086 Removing extra closing brackets 7f81779 Modifing a testcase to exercise SSR Coeff reload 90c2687 Adding FIR SR Asym RTP Coeff Reload for SSR configs. 02d24b3 decimate sym metadata updates c3bb0d9 Merge pull request Xilinx#391 from liyuanz/next f0c7fa5 keep all rst file in src dir 1f6eda3 update rst in next branch 063c467 Merge pull request Xilinx#385 from dbee/polyphase_decomposer f90792a update 4d5f2b4 Merge pull request Xilinx#389 from gordono/next 54e7d7a fix missing include and nets on testbench bwkds compat eb971cf adding missing debug end clause c3c13e1 avoid metadata failure for TP_INTERP == SSR when decomposing 0aeaf16 Merge pull request Xilinx#387 from gordono/next 271d589 correcting metadata check after change to decimator ADL-951 0237d24 correcting window size error traps d5f144f fixes with merge issues 99d8cda Merge branch 'next' of https://gitenterprise.xilinx.com/dbee/xf_dsp into polyphase_decomposer 8546a10 Merge pull request Xilinx#383 from mlechtan/next 34e1ff6 Fixing aie_control_xrt.cpp clang-formatting 7095d10 Fixing Metadata issues wrt to coeff reload check d2203cc Merge pull request Xilinx#377 from uvimalku/ssr_decimate_sym 4f52ca9 Merge pull request Xilinx#382 from mlechtan/next 84393e6 Fixing clang-formatting b75502d Merge branch 'next' into ssr_decimate_sym 451c48c Merge pull request Xilinx#376 from uvimalku/clean-up-graph-utils d985846 Merge branch 'next' into clean-up-graph-utils f9ab13a Merge pull request Xilinx#374 from uvimalku/sr_sym_ssr_metadata 0821e26 Merge branch 'next' into sr_sym_ssr_metadata c86fa4a Merge pull request Xilinx#381 from mlechtan/next 862c7ec Temporarily removing (misconfigured) SSR testcase 5527e1d Merge pull request Xilinx#379 from mlechtan/metadata_coeff_reload 65336bc Merge pull request Xilinx#375 from FaaSApps/fir_decimate_asym_with_dm 6e42dd4 Merge pull request Xilinx#378 from gordono/next 578a9c7 Delete Readme.txt d7e8b6a Reverting iteration count to speed up. b1afac7 fix incorrect naming c7067cc git formatting and perforce sync up 7f036e9 adding tests for decomposer 1c07be5 updated metadata to test SSR and interpolator and decomposer 14077b9 Metadata update wrt header based coeff reload e353e05 Merge branch 'next' of https://gitenterprise.xilinx.com/dbee/xf_dsp into polyphase_decomposer 10d16f2 correction typo in description for fft_window 7736349 correct test case for decimate_asym ssr 8fef74f add modified fir_graph_utils to commit b16bf77 refactor ssr test case dec asym c024481 revert changes fir_dec_hb_graph 4e676de add SSR test cases for decimators 28347d5 ssr support for decimate sym 0948b8b basic tidyup 3bfee87 Setting iteration count to 2 094a3ff Fixing stim type to default 4c2f5f7 modify test case decimate_asym_ssr 692d957 correct output window size sr_sym_ssr ba7d1a6 make common function to convert taps to for suitable to redirect to sr asym 74cf3e3 Reducing iteration count and increasing LSF timeouts 651293d Merge branch 'sr_sym_ssr_metadata' of https://gitenterprise.xilinx.com/uvimalku/xf_dsp into sr_sym_ssr_metadata 4c8781b fir graph utils cleanup 4b239d6 Fixing absoaie_control_xrt to relative path 911df9a Adding host.cpp b3fd0fe Adding FIR (fir_decimate_asym) case with datamover 13b1801 Update multi_params.json 395b0e7 sr sym ssr support when TP_FIR_LEN % TP_SSR != 0 3999ce1 window size check for sym streaming api 7aabd8d sr sym ssr redirect to sr asym d1707fb fir sr sym metadata and makefile changes bd52830 add ssr concept to interp asym makefile gen input 2c2f9f8 remove incorrect check and tidy up 1a356eb reverting interface change to create_connections 3628dad Merge pull request Xilinx#373 from gordono/next c0a559a Merge branch 'next' of https://gitenterprise.xilinx.com/gordono/xf_dsp into next 96911cd increasing stack size for fft_window d3e0b29 fix inconsistent whitespace cd1eefb remove debug print e0e6b9a working basic para_interp_poly=3 case b492110 decomposer logic added syntatically and default case still working d50b367 Merge pull request Xilinx#372 from mlechtan/next a06d7c7 Fixing Metadata config checker for Dec Sym FIR 14f8e12 Merge pull request Xilinx#371 from mlechtan/next 0affcd3 Adding a testcase with dual inputs & header coeff reload. 32cf253 Fix for creating coeff header for dual input streams cases. 34a04f1 Merge pull request Xilinx#369 from mlechtan/next c5dad0a Merge pull request Xilinx#368 from uvimalku/decimate_asym_metadata 1dd7e70 Fix for TP_FIR_LEN % TP_SSR static_assert triggering on hb dec cases. ec9a658 Merge pull request Xilinx#364 from mlechtan/next 559a2a1 metadata for decimate asym e4022af metadata changes for fir interpolate asym 164f363 Delete test.cpp-4f884644 5c5298a Merge pull request Xilinx#366 from uvimalku/decimate_hb_metadata a2df27f get_common_config update abbd044 metadata changes for interpolate hb ssr 5208b51 Merge pull request Xilinx#365 from uvimalku/decimate_hb_metadata c511f90 Correcting pre_build Ref model config a536a65 update common config tcl 16f0f48 SSR metadata updates for decimate hb 8a4b24f Fixing casc_in_type direction. 1013a24 Adding SR ASYM FIR testcases 596b0ed Header based Coefficient Reload for SR Asym FIR. 2363e15 Tidy up comments. c6338a3 Merge branch 'next' of https://gitenterprise.xilinx.com/mlechtan/xf_dsp into next d00e710 Merge pull request Xilinx#363 from uvimalku/interpolate_asym_ssr_tests c38c44e Renaming kernel_rtp_reload to kernel_coeff_reload 5bf5793 Merge pull request Xilinx#357 from yuanqian/next 377e371 Merge pull request Xilinx#361 from gordono/next 286e688 coding style correction for interpolate_asym f340d5d Merge branch 'next' of https://gitenterprise.xilinx.com/gordono/xf_dsp into next f896bc5 Merge branch 'FaaSApps:next' into next 48bd703 increasing stack size a tad bf64256 Merge pull request Xilinx#362 from uvimalku/interpolate_asym_ssr_tests c9dc478 remove todo f7a5935 skip checking output if skip_ref 226218f add ssr test for interpolate asym a4149fd adding generic source file 9294f72 Merge pull request Xilinx#360 from uvimalku/decimate_asym_ssr_test 6cf25c5 added tests for decimate asym ssr 24bbd05 Metadata mods for decimate asym fir f50f518 Merge branch 'FaaSApps:next' into next 267a7fa tayloring stack size for fft_window 44cdf82 Cleeanup fir_decimate_asym.py 04eadc2 Added ssr test for decimate asym 6956fdb Merge pull request Xilinx#359 from dbee/metadata_cleanup cf24b63 fix parameter descriptions 948a21c remove deprecated metrics info 304f910 mat mult has no TP_API 90ad7eb streaming info in info_ports ffbfb32 fix graphname 5f476f7 adding skip flags to interpolate makefile 20bdb79 initial decomposer logic passing first syntax barrier backward compatibly f7c6d17 Merge pull request Xilinx#355 from gordono/next 913d72d Merge pull request Xilinx#358 from uvimalku/interpolate_hb_ssr_tests d320eb6 Remove extra tests 9ae2a35 Merge branch 'interpolate_hb_ssr_tests' of https://gitenterprise.xilinx.com/uvimalku/xf_dsp into interpolate_hb_ssr_tests 26b13a3 Makefile mods to interpolate_hb for ssr b581681 Update multi_params.json 28663ab Makefile changes for interpolate hb ssr c9f6c25 Merge pull request Xilinx#354 from uvimalku/decimate_hb_ssr_tests 7ea6deb rename ladf_api_xrt_swemu to ladf_api_xrt 1ec5cdc addition of candidate AIE-ML AIE2 support for FFT c516168 Merge pull request Xilinx#346 from gordono/next 060ace2 Update multi_params.json fd5d375 Merge pull request Xilinx#353 from uvimalku/decimate_hb_ssr_tests aa6f285 signal name clarification b67e121 Merge branch 'FaaSApps:next' into next ebfda02 added SSR tests for dec hb 367c397 Merge pull request Xilinx#352 from uvimalku/interpolate_asym_ssr 92ba6be matmul Makefile changes 9af5133 a few changes with para poly on the graph to give backwards compatible passes c784ef2 Makefile mods to 2022.2 0586a06 makefile and testbench changes for poly interp 943e4de Merge branch 'polyphase_decomposer' of https://gitenterprise.xilinx.com/dbee/xf_dsp into polyphase_decomposer 3184b83 Merge branch 'FaaSApps:next' into polyphase_decomposer ea19259 Merge pull request Xilinx#351 from uvimalku/interpolate_asym_ssr 4ceb3d1 modify fir common traits with updated function for decimate asym 831d738 SSR changes for decimate_asym 254cd68 SSR changes for decimate_hb a6c867c add changes to hpp files f294868 Merge pull request Xilinx#350 from mlechtan/next b163e54 FIR SR Asym Ref model updated with support for Header based Coeff Reload e973f8c FIR SR Asym Metadata update 62ae537 Script tidy up 3fc1819 Scripts update to support Header based Coeff Reload. 3bcb7ea correcting clause for addition of weights parameter at end of config generaton 956e6b8 fix for dyn pt size bug, elaboration of location constraints and use of single buffer for large dynamic cases to avoid memory spill 021cdc0 decomposer testbench changes and ref model on interpolator de8c2aa added port info and updated generate graph iwth SSR and para poly 9607808 Decomposer metadata working for interpolate_asym, except gen_graph 2ad35a1 Merge pull request Xilinx#345 from dbee/metadata_cleanup f893515 adding correct port info and dual out to generate_graph 12174fc Update type to be unsigned 4caa72d Merge pull request Xilinx#344 from dbee/matadata_update_general fc4796f Merge branch 'metadata_dds_mixer' into matadata_update_general 17f2a77 already moved to common file c6c457b functions are used in matrix mult ba50507 Merge branch 'next' into matadata_update_general - fft window changes bb59dd3 add testing of metadata to makefiles b398e99 add initial offset d7fb4ad adding phaseInc 3c854a3 basic dds mixer metadata 542c789 Merge branch 'metadata_update_matmult' into matadata_update_general 08d9ddb Merge pull request Xilinx#343 from gordono/next f8203db mering fft and fft_window changes c8e2c46 Merge pull request Xilinx#4 from FaaSApps/next 2214611 Merge branch 'next' into next edcc175 fixing metadata test prebuild stage c4bfb1f Merge pull request Xilinx#337 from dbee/metadata_update_fft 6067150 Merge branch 'metadata_update_fft' of https://gitenterprise.xilinx.com/dbee/xf_dsp into metadata_update_fft 1dc717a fix missing comma from merge and regen makefile 2a1ab29 This has been made common b8ad746 Merge branch 'FaaSApps:next' into next cc3d1a1 small tidy up of magic number b5e3439 fix typo 5802263 add extra gitignore 31dcdc3 makefile update 14dee3e update multi_params to be correct param names e8ae29b update makefile and decription.json for metadata checking bcca9e5 adding fft_window metadata bbf2282 adding mat mult to tests but also allowing an argument to just test one element. 7dc6e4e Adding validating logic to matmult 759528d Merge pull request Xilinx#340 from changg/22.2_mks e6d498b Merge pull request Xilinx#341 from changg/22.1_mks_update1 73751b2 fix mk 886da71 22.2 mk update 0751164 Create fft_window.py 0808470 Create fft_window.json 7ead7be Merge pull request Xilinx#339 from gordono/next acf030e Merge branch 'next' of https://gitenterprise.xilinx.com/gordono/xf_dsp into next a2fdbb3 avoiding mapper error e54d823 Merge branch 'FaaSApps:next' into next 87c55b9 adding aiesim tests again b944e56 Merge pull request Xilinx#328 from gordono/next 525d482 Update multi_params.json eefc7c7 Adding FFT window documentation first pass. 6d97323 addition of dynamic mode for FFT window, correction of pass by value array and move to multiple tables construction for dyn mode 79a056f Merge branch 'FaaSApps:next' into next 14f4d13 initial creation without validators d968535 add comma that was missing after merge f0b43da adding fft test 24e4017 create config and test entry 5441754 Sync recent cahgnes on metadata d111938 Merge pull request Xilinx#332 from dbee/metadata_update_other_fir 616761e Merge pull request Xilinx#20 from FaaSApps/sync_changes f469d88 Merge branch 'metadata_update_fft' into sync_changes 4092e3b add gitignore for generated graph files 90444db Fix inconsistencies on decimator and lanes 3e843a5 FFT Metadata Creation a095131 rearranging some common functions 0383758 Merge branch 'next' into metadata_update_other_fir 63abc28 Merge pull request Xilinx#18 from justusr/debug_practise 6fb8a90 Resolve jenkins errors: remove multipleInterpolationRateCheck from fir_resampler, set the default of TP_API to window(=0), change firLengthMax to 1024 and firLengthMin to 1 in aie_common.py in line with c++ implementation. Also add __pycache__ to gitignore. e422bef Merge pull request Xilinx#335 from mlechtan/next c30dc52 Consolidating x86sim runs with missing commands and/or tolerance options dd97917 Merge pull request Xilinx#334 from mlechtan/next 88c3825 Updating float testcase with diff tolerance 4280228 Fix for FIR Decimate Asym High DFs. Adding testcases to for various data type combinations. 471935a Expected changes for FFT json 643295d Expected json file for fft d94225a by default have a FIR common file, will incrementally port actual common stuff into generic common file. 84de6fe Merge pull request Xilinx#17 from dbee/attempt-to-resolve-conflict ca4be5f Merge branch 'metadata_update_other_fir' into attempt-to-resolve-conflict f2719d5 Merge pull request Xilinx#16 from FaaSApps/next a64c8e8 Fixing search paths 965809c Ease of use enhancements to config checker script d0f5a49 Moving some functions into common area 1b5c8ff Bash script to quickly validate all the configs 6a4bc9c remove vector length from json - CR1131133 a6be5be general Makefile update 796e0aa resampler updates 10618a4 Merge pull request Xilinx#331 from mlechtan/next e70aebb Disabling FIR Decimate HB SSR testcase temporarily. 8a9cc48 Merge pull request Xilinx#330 from mlechtan/next d9f008f Adding extra testbench driver to FIR Interpolate HB 4e7e7af Updating example's graph ports to arrays 2b89496 Removing __AIEARCH__ and __AIENGINE__ macro definition from kernel source. 4a2ea76 Missed reference model updates efa0414 FIR Graphs parameter structs reorg. 9ecd53d Merge pull request Xilinx#18 from uvimalku/decimate_hb_ssr_support b88cecc adding documentation for fft window 0ab1246 Add modified window sizes for ssr 25bd88e Merge branch 'FaaSApps:next' into next 6662272 adding dyn parallel test 12f871c Merge pull request Xilinx#327 from gordono/next 8f5650a correcting passing of window_vsize to x86 ff334ab setting simpler default and removing aiecompiler for now d7973c5 makefile changes for preproc args 1e2c456 Update description.json with ssr preproc args 5e3ebad Merge branch 'next' of https://gitenterprise.xilinx.com/gordono/xf_dsp into next 2a0dfd7 adding tests for fft_window 4a78304 graph utils bug 81c9259 Merge branch 'FaaSApps:next' into next 462d61d addition of checkin test for fft_window and consequent changes to description.json and helper.mk etc to get this flow to work 413b0a8 add graph_utils mods for decimate hb ssr e678531 SSR support for decimate_hb c03629b Merge pull request Xilinx#323 from uvimalku/move-graph-utils-with-sr-asym 9f400e2 Merge branch 'next' of https://gitenterprise.xilinx.com/gordono/xf_dsp into next 65f67fb Merge pull request Xilinx#324 from mlechtan/next 3ce5b06 Fixing clang-formatting bf9c200 introducing fft_window library element dea0107 Adding cases for cint32/cint with 2 outputs a68db4d Adding DUAL_IP cases + cint32/cint32 case e19a1bc Fix for FIR's stream writing with cint32/cint32 and 2 outputs a14e862 change default templated class argument to sr::asym 4b764a4 remove incorrect change in previous commit d69379b move create_kernels and ssr_kernels class into graph utils - and workaround for the graph within graph bug a7d8310 Merge pull request Xilinx#322 from mlechtan/next 42caac8 Merge branch 'FaaSApps:next' into next 44cd998 Merge pull request Xilinx#320 from gordono/next 8902ac0 Merge pull request Xilinx#17 from gordono/next c291ef6 Making FIR's kernel members public 431b1ad correcting x86 calls to split_zip for widgets dceab45 syntax fixes and dds_mixer ssr_split zip argument tidy a499b22 more corrections to description.json syntax 1092ad4 fixing ssr arguments 5ddf915 adding makefiles this time 44e61ec fixing HEADER BYTES in widget and equation in FFT for window size d3b3660 removing more stop on deadlocks f53c5ec corrections to window size for firs in makefile, header bytes for widgets and equation in fft f366c0f removing stop on deadlock 4331f5f updating description.jsons for changes to ssr_split_zip arguments forced by header on FFT and rewrite of script f8525ff decimate sym updates ac6415f update to helper.mk for window size and ssr_split_zip arguments df41e3c Merge branch 'next' of https://gitenterprise.xilinx.com/gordono/xf_dsp into next f4b11e6 updating make for ssr_split_zip parameters 36547e1 Update graph_utils.hpp 218efc9 decimate asym changes e2ed18a Merge branch 'next' into next 1d3cdbc dynamic point size with SSR for FFT d8c850a Updating Makefiles vwith 2022.2 vck190 platform 0abe73b forgot config 30f2184 Changes for interpolate_asym 61459ca interpolate_hb metadata updates 1ff2260 description.json update and makefile f1e232b decimate hb first pass valid c926610 changes for sr_sym and some fixes in sr_Asym f5f4dc7 Initial copy from sr_asym 3add5a4 Pulled some changes into common ca64244 Got metadata checker integrated into makefile prebuild d0a2d44 Expected changes for sr_asym 1b8e9c3 Merge branch 'metadata_update' of https://gitenterprise.xilinx.com/dbee/xf_dsp into metadata_update 18238ba updated files before making some functions common 6c1757c change 2022.1_stable_latest to 2022.2_stable_latest b566be7 Merge branch 'FaaSApps:next' into metadata_update c8d1dac initial checkin from sumanta repo e05cee7 Merge pull request Xilinx#317 from changg/fix_mks 73bf7b3 update pl makefils 6ed11ec Update api-reference.rst 7a61b1a Update index.rst Co-authored-by: sdausr <[email protected]>
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AI_Engine_Development/Design_Tutorials/01-aie_lenet_tutorial
** the issue **
Follow the instructions in the GitHub, I can run hw_emu in the QEMU environment. But when I make the project with TARGET=hw and use the sd card image to boot the VCK190 board, the /mnt folder doesn't have any files. Could you help to seek out where is the bug? Thanks a lot for your attention.
Some unusual outputs during booting:
** Environment: **
The text was updated successfully, but these errors were encountered: