Updated 03-rtl_stream_kernel_integration image references for 2021.2 (#…

…384)

* Changed landing page to have all versions available

* Corrected image reference issues in 03-rtl_stream_kernel_integration

* Updated 03-rtl_stream_kernel_integration image references

---------

Co-authored-by: Ryan Vergel <[email protected]>

2021-2/build/html/_sources/docs/Hardware_Acceleration/Design_Tutorials/03-rtl_stream_kernel_integration/README.md.txt

@@ -1,6 +1,6 @@
-<table class="sphinxhide">
+<table class="sphinxhide">
  <tr>
-   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>Vitis™ Application Acceleration Development Flow Tutorials</h1>
+   <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Vitis™ Application Acceleration Development Flow Tutorials</h1>
    </td>
  </tr>
  <tr>
@@ -19,6 +19,8 @@ This tutorial demonstrate the design flow for an example mixed kernels hardware
 <img src="./doc/images/alpha_mixing.jpg" alt="Alpha Mixing" >
 </div>
 
+![]()
+
 <br/><br/>
 
 The hardware design includes three kernels: *rtc_gen*, *alpha_mix*, and *strm_dump*. These kernels are directly connected together using AXI stream link. The topology of the design is shown in the figure below. 
@@ -27,6 +29,8 @@ The hardware design includes three kernels: *rtc_gen*, *alpha_mix*, and *strm_du
 <img src="./doc/images/topo.png" alt="Topology" >
 </div>
 
+![]()
+
 The designs have been verified with following software/hardware environment and tool chain version:
 * Operating System
   * Redhat/CentOS 7.4 - 7.9
@@ -76,10 +80,7 @@ The directory struction and brief explainations are as below.
 
 The character size in the font library is 240 (height) by 160 (width) pixels, and the font library includes 11 characters, i.e. digits 0-9 and colon. Refer to the image below for the font library contents.  
 
-<div align="center">
-<img src="./doc/images/font_lib.png" alt="Font Library" >
-</div>
-<br/><br/>
+![Font Library](./doc/images/font_lib.png)
 
 Each pixel in the font library is represented with 4-bit, which is actually the opacity value for each pixel. When output through AXI stream port, the 4-bit opacity value will be expanded to 8-bit by left shifting 4-bit then add 15 (i.e., expand 0xB to 0xBF). The opacity value will be used by the downstream alpha-mixing kernel to generate time digit with color setting. The font image data size for single chracter is:
 ~~~
@@ -94,9 +95,8 @@ The total font image library size is:
 
 *rtc_gen* support two time format: one is with centi-second, namely HOUR:MIN:SEC:CENTISEC, including 11 characters; the other is without centi-second, namely HOUR:MIN:SEC, including 8 chracters. The time format is set in kernel arguments. Refer to the figures below for examples of the two output time format.
 
-<div align="center">
-<img src="./doc/images/time_format.png" alt="Time Format" >
-</div>
+
+![Time Format](./doc/images/time_format.png)
 
 The *rtc_gen* kernel has three bus interfaces:
 + AXI-Lite slave interface for kernel argument and control
@@ -105,9 +105,8 @@ The *rtc_gen* kernel has three bus interfaces:
 
 The kernel is composed of three blocks: *rtc_gen_axi_read_master* for AXI master based font library reading, *rtc_gen_control_s_axi* for AXI slave based kernel arguments and control, and *rtc_gen_core* for core kernel function and AXI stream output. *rtc_gen_axi_read_master* is a standard block generated by Vitis/Vivado RTL Kernel Wizard. *rtc_gen_control_s_axi* is also a generated block, but we need to make some modifications to it to add time value read-out function.
 
-<div align="center">
-<img src="./doc/images/rtc_gen_block.png" alt="rtc_gen Block" >
-</div>
+![rtc_gen Block](./doc/images/rtc_gen_block.png)
+
 
 When triggered by the host, the kernel will read time value from internel real-time-clock, and output a frame of time image corresponding to the time value.
 
@@ -130,14 +129,14 @@ Please read [RTC_GEN RTL Kernel Creation](./doc/rtc_gen_tutorial.md) for more de
 ## HLS C Kernel: alpha_mix (XO)
 
 The kernel *alpha_mix* finishes follow tasks in order:
+
 * Receive the clock digit image from *rtc_gen* kernel via AXI stream port
 * Resize the clock digit image with Vitis Vison Library resize function
 * Load the background image from global memory, then execute alpha mixing with the clock digit image
 * Send out the mixed image via AXI stream port
 
-<div align="center">
-<img src="./doc/images/alpha_flow.png" alt="alpha_mix flow" >
-</div>
+![alpha_mix flow](./doc/images/alpha_flow.png)
+
 
 The *alpha_mix* kernel has four bus interfaces:
 
@@ -167,9 +166,7 @@ Following table summarized the arguments used by *alpha_mix* kernel. Please note
 
 You could refer to below figure for the meaning of some kernel arguments.
 
-<div align="center">
-<img src="./doc/images/alpha_arg.png" alt="alpha_mix kernel arguments" >
-</div>
+![alpha_mix kernel arguments](./doc/images/alpha_arg.png)
 
 Please read [ALPHA_MIX HLS C Kernel Creation](./doc/alpha_mix_tutorial.md) for more details of the HLS C kernel *alpha_mix*.
 
@@ -191,17 +188,15 @@ Following table summarizes the arguments used by *strm_dump* kernel.
 
 This is a simple test system for *rtc_gen* kernel, which integrates two kernels: *rtc_gen* and *strm_dump*, which are connected together using AXI stream bus. Refer to the following connection diagram on U50 platform. According to the different building target (hw or hw_emu), two XCLBIN files will be generated.
 
-<div align="center">
-<img src="./doc/images/rtc_gen_test_diagram.png" alt="rtc_gen_test Diagram" >
-</div>
+![rtc_gen_test Diagram](./doc/images/rtc_gen_test_diagram.png)
+
 
 ### rtc_alpha_hw.xclbin / rtc_alpha_hw_emu.xclbin
 
 This is the fully implemented system, which integrated all the three kernels: *rtc_gen*, *alpha_mix* and *strm_dump*, which are connected together via AXI stream bus. Please note the function of the kernel *strm_dump* is very easy to be merged into *alpha_mix* kernel. We separated the *strm_dump* kernel here just to demonstrate the kernel-to-kernel AXI stream connection functionality. Refer to the following connection diagram on U50 platform. According to the different building target (hw or hw_emu), two XCLBIN files will be generated.
 
-<div align="center">
-<img src="./doc/images/rtc_alpha_diagram.png" alt="rtc_alpha Diagram" >
-</div>
+![rtc_alpha Diagram](./doc/images/rtc_alpha_diagram.png)
+
 
 ## Test Program
 

2021-2/build/html/_sources/docs/Hardware_Acceleration/Design_Tutorials/03-rtl_stream_kernel_integration/doc/alpha_mix_tutorial.md.txt

@@ -32,9 +32,7 @@ void alpha_mix(hls::stream<ap_axiu<64, 0, 0, 0>> &time_img_input,   // time imag
 
 Following is the sub-function and data flow diagram for *alpha_mix* kernel.
 
-<div align="center">
-<img src="./images/alpha_mix_flow.png" alt="alpha_mix flow" >
-</div>
+![alpha_mix flow](./images/alpha_mix_flow.png)
 
 In the diagram, the sub-functions filled with red are from Vitis Vision Library, and those with blue are hand-written. *xf::cv::Mat* is the counterpart for *cv::Mat* in OpenCV software library, it is very useful for handling image data. In the hardware implementation, if we want to handle the image with in-order pixel level (no need to randomly access the pixel data), we can use *#pragma HLS stream* to indicate the compiler to map the *xf::cv::Mat* object to array. This is the case for our *alpha_mix* kernel. Many functions in Vitis Vision Library support *xf::cv::Mat* as the input and output data. In the HLS C code, we can use for-loop to process data in *xf::cv::mat* stream easily, you can refer to the source code of sub-function *mixing* for alpha-mixing operation applied to the input and output *xf::cv::Mat* objects.
 

2021-2/build/html/_sources/docs/Hardware_Acceleration/Design_Tutorials/03-rtl_stream_kernel_integration/doc/hw_emu_tutorial.md.txt

@@ -23,9 +23,7 @@ Let's take the Hardware Emulation result of *rtc_gen_test* on U200 card as an ex
 vitis_analyzer rtc_gen_test_hw_emu.xclbin.run_summary
 ```
 
-<div align="center">
-<img src="./images/hw_emu_waveform.PNG" alt="Hardware Emulation Waveform" >
-</div>
+![Hardware Emulation Waveform](./images/hw_emu_waveform.PNG)
 
 You can also open the waveform database with the Vivado logic simulator `xsim`
 

2021-2/build/html/_sources/docs/Hardware_Acceleration/Design_Tutorials/03-rtl_stream_kernel_integration/doc/profile_tutorial.md.txt

@@ -21,19 +21,15 @@ vitis_analyzer rtc_alpha_hw.xclbin.run_summary
 
 Guidance includes message for reported violations, a brief suggested resolution, and a detailed resolution provided as a web link. The rules are generic rules based on an extensive set of reference designs, thus might not be applicable for every design. You need to understand the specific guidance rules and take appropriate action based on your specific algorithm and requirements.
 
-<div align="center">
-<img src="./images/hw_guidance.PNG" alt="Hardware Run Guidance" >
-</div>
+![Hardware Run Guidance](./images/hw_guidance.PNG)
 
 ## Platform and System Diagrams
 
 The Platform and System Diagrams display a representation of the platform resources and the kernel code integrated onto the platform. The System Diagram shows memory banks or PLRAMs used by the XCLBIN, how the function arguments of CUs are connected to AXI4 interfaces. It includes profile data from the run, and the resource information from the bottom table can also be displayed in a box next to each kernel or CU in the System Diagram. 
 
 Please use upper right **Settings** button to display or hide Unused Memory, Interface Ports, Profile Info, and Resource info.
 
-<div align="center">
-<img src="./images/hw_sys_diagram.PNG" alt="Hardware System Diagram" >
-</div>
+![Hardware System Diagram](./images/hw_sys_diagram.PNG)
 
 ## Profile Summary
 
@@ -49,23 +45,17 @@ rtc_gen_test_$(TARGET).xclbin: $(XOS_RTC_GEN_TEST)
 	v++ -l $(XOCCFLAGS) $(XOCCLFLAGS) --config xclbin_rtc_gen_test.ini --profile_kernel data:all:all:all  -o $@ $(XOS_RTC_GEN_TEST)
 ```
 
-<div align="center">
-<img src="./images/hw_profile_summary.PNG" alt="Profile Summary" >
-</div>
+![Profile Summary](./images/hw_profile_summary.PNG)
 
 Even without `--profile_kernel` option added while generating XCLBIN files, most of the profiling reports are still available, only few sections like the Kernel Data Transfers will show no data.
 
-<div align="center">
-<img src="./images/no_kernel_data.PNG" alt="No Kernel Data" >
-</div>
+![No Kernel Data](./images/no_kernel_data.PNG)
 
-##  Application Timeline
+## Application Timeline
 
-Application Timeline collects and displays host and kernel events on a common timeline, it helps to understand and visualize the overall health and performance of the systems. The graphical display makes it easy to discover issues regarding kernel synchronization and efficient concurrent execution. 
+Application Timeline collects and displays host and kernel events on a common timeline, it helps to understand and visualize the overall health and performance of the systems. The graphical display makes it easy to discover issues regarding kernel synchronization and efficient concurrent execution.
 
-<div align="center">
-<img src="./images/hw_timeline.PNG" alt="Application Timeline" >
-</div>
+![Application Timeline](./images/hw_timeline.PNG)
 
 If you are looking for more details of Profiling and how to use *Vitis Analyzer*, check on [Profiling the Application](https://www.xilinx.com/html_docs/xilinx2020_1/vitis_doc/profilingapplication.html) from Vitis online documentation. 
 

2021-2/build/html/_sources/docs/Hardware_Acceleration/Design_Tutorials/03-rtl_stream_kernel_integration/doc/rtc_gen_tutorial.md.txt

@@ -31,6 +31,8 @@ Thus we generalize the top level design specification for *rtc_gen* kernel as be
 <img src="./images/rtc_gen_block.png" alt="RTL Kernel" >
 </div>
 
+![RTL Kernel](./images/rtc_gen_block.png)
+
 <br/>
 
 ## Use RTL Kernel Wizard to Create Kernel Frame
@@ -48,67 +50,51 @@ vivado &
 
 We create a new RTL project named *rtc_gen_kernel* in the just created *vivado_project* directory. During the part selection page, select **Alveo U200 Data Center Accelerator Card*.
 
-<div align="center">
-<img src="./images/rtl_kernel_wiz_1.png" alt="RTL Kernel" >
-</div>
+![RTL Kernel](./images/rtl_kernel_wiz_1.png)
 
 <br/>
 
 When the project is created, in the Flow Navigator, click the IP catalog command, type RTL Kernel in the IP catalog search box, then double-click RTL Kernel Wizard to launch the wizard.
 
 In the *General Settings* tab of the RTL Kernel Wizard, set the kernel name to **rtc_gen**, set the kernel vendor to **xilinx.com**, change the *has reset* option to value 1, refer to below snapshot.
 
-<div align="center">
-<img src="./images/rtl_kernel_wiz_2.png" alt="RTL Kernel" >
-</div>
+![RTL Kernel](./images/rtl_kernel_wiz_2.png)
 
 <br/>
 
 In the *Scalars* tab, configure the kernel arguments as our design specification. Refer to the **Control Register** table and below snapshot. Please note **read_addr** register is not considered scalar argument as AXI master pointer, so we don't need to configure it in this tab. We are using **uint** as argument type here, though all these bit might not be used.
 
-<div align="center">
-<img src="./images/rtl_kernel_wiz_3.png" alt="RTL Kernel" >
-</div>
+![RTL Kernel](./images/rtl_kernel_wiz_3.png)
 
 <br/>
 
 In the *Global Memory* tab, configure the AXI master interfaces parameters according to our design specification. Name the AXI master interface to **fontread_axi_m**, change the width to 4 bytes (32-bit), and set the relating argument name to **read_addr**. Refer to below snapshot.
 
-<div align="center">
-<img src="./images/rtl_kernel_wiz_4.png" alt="RTL Kernel" >
-</div>
+![RTL Kernel](./images/rtl_kernel_wiz_4.png)
 
 <br/>
 
 In the *Streaming interfaces* tab, set the number of AXI4-Sttream interfaces to 1, name it to **dataout_axis_m**, set the mode the **Master**, and set the width to 8 bytes (64-bit). Refer to below snapshot.
 
-<div align="center">
-<img src="./images/rtl_kernel_wiz_5.png" alt="RTL Kernel" >
-</div>
+![RTL Kernel](./images/rtl_kernel_wiz_5.png)
 
 <br/>
 
 Finally review the summary page of the wizard, and click *OK* button to generate the RTL kernel top level framework. 
 
-<div align="center">
-<img src="./images/rtl_kernel_wiz_6.png" alt="RTL Kernel" >
-</div>
+![RTL Kernel](./images/rtl_kernel_wiz_6.png)
 
 <br/>
 
 For the next "Generate Output Products" pop-up window, just click *Skip* button close the window. Now you can see the *rtc_gen.xci* file in the *Design Sources* group of *Sources* view. Right click the *rtc_gen.xci* file, select *Open IP Example Design*.
 
-<div align="center">
-<img src="./images/rtl_kernel_wiz_7.png" alt="RTL Kernel" >
-</div>
+![RTL Kernel](./images/rtl_kernel_wiz_7.png)
 
 <br/>
 
 In the *Open IP Example Design* pop-up window directly click *OK* button, then another project named *rtc_gen_ex* will be created in *./vivado_project* directory and open automatically in another Vivado session. We will use project *rtc_gen_ex* as the major working project to finish the *rtc_gen* kernel development.
 
-<div align="center">
-<img src="./images/rtl_kernel_wiz_8.png" alt="RTL Kernel" >
-</div>
+![RTL Kernel](./images/rtl_kernel_wiz_8.png)
 
 <br/>
 
@@ -130,9 +116,7 @@ rtc_gen.v
 
 In the *Sources* view, *Hierarchy* tab, we can see the HDL file hierarchy. Now we have finished the kernel framework creation.
 
-<div align="center">
-<img src="./images/rtl_kernel_wiz_9.png" alt="RTL Kernel" >
-</div>
+![RTL Kernel](./images/rtl_kernel_wiz_9.png)
 
 <br/>
 
@@ -165,9 +149,7 @@ We will use following generated RTL files in our *rtc_gen* kernel:
 
 In addition to these five files, we could also refer to *rtc_gen_example_vadd.sv* for the connection of AXI read master. For AXI stream port, it is simple and we don't need the example for reference. For *rtc_gen* kernel, a Verilog file *rtc_gen_core.v* is created to finish the core function of the kernel. The function diagram of *rtc_gen_core* is shown in following diagram.
 
-<div align="center">
-<img src="./images/rtl_kernel_wiz_10.png" alt="RTL Kernel" >
-</div>
+![RTL Kernel](./images/rtl_kernel_wiz_10.png)
 
 <br/>
 
@@ -185,9 +167,7 @@ To make the core source code directory clean, we put all the necessary generated
 
 Now we remove all the existing Verilog/SystemVerilog source codes (except for thos in *IP* group) from the *rtc_gen_ex* project in Vivado, then add the files in *./rtc_gen/src* to the project (*rtc_gen_tb.sv* for *Simulation-Only Sources*, other files for *Design Sources*). Thus you can see the design hierarchy as below snapshot, and we finish the coding for kernel *rtc_gen*.
 
-<div align="center">
-<img src="./images/rtl_kernel_wiz_11.png" alt="RTL Kernel" >
-</div>
+![RTL Kernel](./images/rtl_kernel_wiz_11.png)
 
 <br/>
 
@@ -197,9 +177,7 @@ Now you can simulation the design and go through normal RTL design flow with sta
 
 After you confirm the design is OK, select *Generate RTL Kernel* from *Flow* Menu, then select *Sources-only kernel* in the pop-up window, click *OK* button to finish the *rtc_gen* RTL kernel creation.
 
-<div align="center">
-<img src="./images/rtl_kernel_wiz_12.png" alt="RTL Kernel" >
-</div>
+![RTL Kernel](./images/rtl_kernel_wiz_12.png)
 
 <br/>