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Merge pull request #852 from vijayank88/flow_variable_update
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Flow variable update
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@maliberty
maliberty authored Mar 8, 2023
2 parents 0893cc8 + 388d320 commit 846b6d2
Showing 1 changed file with 75 additions and 52 deletions.
127 changes: 75 additions & 52 deletions docs/user/FlowVariables.md
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Expand Up @@ -38,50 +38,51 @@ Note:
- N/A indicates that the variable/files is not supported currently.


| **Configuration Variable** | **sky130hd** | **sky130hs** | **nangate45** | **asap7** |
|--------------------------------------|--------------|--------------|---------------|-----------|
| Library Setup | | | | |
| `PROCESS` | = | = | = | = |
| `TECH_LEF` | = | = | = | = |
| `SC_LEF` | = | = | = | = |
| `LIB_FILES` | = | = | = | = |
| `GDS_FILES` | = | = | = | = |
| `DONT_USE_CELLS` | = | = | = | = |
| Synthesis | | | | |
| `LATCH_MAP_FILE` | = | = | = | = |
| `CLKGATE_MAP_FILE` | = | = | = | = |
| `ADDER_MAP_FILE` | ?= | ?= | ?= | ?= |
| `TIEHI_CELL_AND_PORT` | = | = | = | = |
| `TIELO_CELL_AND_PORT` | = | = | = | = |
| `MIN_BUF_CELL_AND_PORTS` | = | = | = | = |
| `ABC_CLOCK_PERIOD_IN_PS` | ?= | ?= | ?= | ?= |
| `ABC_DRIVER_CELL` | = | = | = | = |
| `ABC_LOAD_IN_FF` | = | = | = | = |
| Floorplan | | | | |
| `PLACE_SITE` | = | = | = | = |
| `MAKE_TRACKS` | = | = | = | = |
| `TAPCELL_TCL` | = | = | = | = |
| `MACRO_PLACE_HALO` | ?= | ?= | ?= | ?= |
| `MACRO_PLACE_CHANNEL` | ?= | ?= | ?= | ?= |
| `PDN_CFG` | ?= | ?= | ?= | ?= |
| `IO_PLACER_H` | = | = | = | = |
| `IO_PLACER_V` | = | = | = | = |
| Placement | | | | |
| `CELL_PAD_IN_SITES_GLOBAL_PLACEMENT` | ?= | ?= | ?= | ?= |
| `CELL_PAD_IN_SITES_DETAIL_PLACEMENT` | ?= | ?= | ?= | ?= |
| `PLACE_DENSITY` | ?= | ?= | ?= | ?= |
| `WIRE_RC_LAYER` | = | = | = | = |
| Clock Tree Synthesis | | | | |
| `CTS_BUF_CELL` | = | = | = | = |
| `FILL_CELLS` | = | = | = | = |
| `CTS_BUF_DISTANCE` | N/A | N/A | N/A | = |
| Routing | | | | |
| `MIN_ROUTING_LAYER` | = | = | = | = |
| `MAX_ROUTING_LAYER` | = | = | = | = |
| `FASTROUTE_TCL` | ?= | ?= | ?= | N/A |
| `RCX_RULES` | = | = | = | = |
| `KLAYOUT_TECH_FILE` | = | = | = | = |
| `FILL_CONFIG` | = | = | N/A | N/A |
| **Configuration Variable** | **sky130hd** | **sky130hs** | **nangate45** | **asap7** | **gf180** |
|--------------------------------------|--------------|--------------|---------------|-----------|-----------|
| Library Setup | | | | | |
| `PROCESS` | = | = | = | = | = |
| `CORNER` | N/A | N/A | N/A | ?= | ?= |
| `TECH_LEF` | = | = | = | = | = |
| `SC_LEF` | = | = | = | = | = |
| `LIB_FILES` | = | = | = | = | = |
| `GDS_FILES` | = | = | = | = | = |
| `DONT_USE_CELLS` | = | = | = | = | = |
| Synthesis | | | | | |
| `LATCH_MAP_FILE` | = | = | = | = | = |
| `CLKGATE_MAP_FILE` | = | = | = | = | = |
| `ADDER_MAP_FILE` | ?= | ?= | ?= | ?= | ?= |
| `TIEHI_CELL_AND_PORT` | = | = | = | = | = |
| `TIELO_CELL_AND_PORT` | = | = | = | = | = |
| `MIN_BUF_CELL_AND_PORTS` | = | = | = | = | = |
| `ABC_CLOCK_PERIOD_IN_PS` | ?= | ?= | ?= | ?= | ?= |
| `ABC_DRIVER_CELL` | = | = | = | = | = |
| `ABC_LOAD_IN_FF` | = | = | = | = | = |
| Floorplan | | | | | |
| `PLACE_SITE` | = | = | = | = | = |
| `MAKE_TRACKS` | = | = | = | = | = |
| `TAPCELL_TCL` | = | = | = | = | = |
| `MACRO_PLACE_HALO` | ?= | ?= | ?= | ?= | ?= |
| `MACRO_PLACE_CHANNEL` | ?= | ?= | ?= | ?= | ?= |
| `PDN_CFG` | ?= | ?= | ?= | ?= | ?= |
| `IO_PLACER_H` | = | = | = | = | ?= |
| `IO_PLACER_V` | = | = | = | = | ?= |
| Placement | | | | | |
| `CELL_PAD_IN_SITES_GLOBAL_PLACEMENT` | ?= | ?= | ?= | ?= | ?= |
| `CELL_PAD_IN_SITES_DETAIL_PLACEMENT` | ?= | ?= | ?= | ?= | ?= |
| `PLACE_DENSITY` | ?= | ?= | ?= | ?= | ?= |
| `WIRE_RC_LAYER` | = | = | = | = | = |
| Clock Tree Synthesis | | | | | |
| `CTS_BUF_CELL` | = | = | = | = | = |
| `FILL_CELLS` | = | = | = | = | = |
| `CTS_BUF_DISTANCE` | N/A | N/A | N/A | = | = |
| Routing | | | | | |
| `MIN_ROUTING_LAYER` | = | = | = | = | ?= |
| `MAX_ROUTING_LAYER` | = | = | = | = | ?= |
| `FASTROUTE_TCL` | ?= | ?= | ?= | N/A | N/A |
| `RCX_RULES` | = | = | = | = | = |
| `KLAYOUT_TECH_FILE` | = | = | = | = | = |
| `FILL_CONFIG` | = | = | N/A | N/A | N/A |


### Library Setup
Expand All @@ -90,6 +91,7 @@ Note:
| Variable | Description |
|------------------|------------------------------------------------------------------------------------------------------------------------------------------------------|
| `PROCESS` | Technology node or process in use. |
| `CORNER` | Library to select based on corner BC/TC/WC. |
| `TECH_LEF` | A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements. |
| `SC_LEF` | Path to technology standard cell LEF file. |
| `GDS_FILES` | Path to platform GDS files. |
Expand All @@ -102,6 +104,7 @@ Note:

| Variable | Description |
|--------------------------|--------------------------------------------------------------------------------------------|
| `SYNTH_HIERARCHICAL` | Enable to Synthesis hierarchically, otherwise considered flat synthesis. |
| `LATCH_MAP_FILE` | List of latches treated as a black box by Yosys. |
| `CLKGATE_MAP_FILE` | List of cells for gating clock treated as a black box by Yosys. |
| `ADDER_MAP_FILE` | List of adders treated as a black box by Yosys. |
Expand All @@ -118,42 +121,61 @@ Note:

| Variable | Description |
|-----------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| `FLOORPLAN_DEF` | Use the DEF file to initialize floorplan. |
| `PLACE_SITE` | Placement site for core cells defined in the technology LEF file. |
| `TAPCELL_TCL` | Path to Endcap and Welltie cells file. |
| `RTLMP_FLOW` | Enable the Hierarchical RTLMP flow. By default it is disabled. |
| `MACRO_PLACEMENT` | Specifies the path of a file on how to place certain macros manually using read_macro_placement. |
| `MACRO_PLACEMENT_TCL` | Specifies the path of a TCL file on how to place certain macros manually. |
| `MACRO_PLACE_HALO` | horizontal/vertical halo around macros (microns). |
| `MACRO_PLACE_CHANNEL` | horizontal/vertical channel width between macros (microns). |
| `MACRO_BLOCKAGE_HALO` | Blockage width overridden from default calculation. |
| `PDN_CFG` | File path which has a set of power grid policies used by `pdn` to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps. |
| `MAKE_TRACKS` | Tcl file that defines add routing tracks to a floorplan. |
| `IO_PLACER_H` | The metal layer on which to place the I/O pins horizontally (top and bottom of the die). |
| `IO_PLACER_V` | The metal layer on which to place the I/O pins vertically (sides of the die). |
| `GUI_NO_TIMING` | Skip loading timing for a faster GUI load. |


### Placement


| Variable | Description |
|--------------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------|
| `HAS_IO_CONSTRAINTS` | Skip the initial non-IO based global placement if IO constraints are present. |
| `CELL_PAD_IN_SITES_GLOBAL_PLACEMENT` | Cell padding on both sides in site widths to ease routability during global placement. |
| `CELL_PAD_IN_SITES_DETAIL_PLACEMENT` | Cell padding on both sides in site widths to ease routability in detail placement. |
| `PLACE_DENSITY` | The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread. |
| `PLACE_DENSITY_LB_ADDON` | Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists. |
| `REPAIR_PDN_VIA_LAYER` | Remove power grid vias which generate DRC violations after detailed routing. |
| `GLOBAL_PLACEMENT_ARGS` | Use additional tuning parameters during global placement other than default args defined in gloabl_place.tcl. |
| `ENABLE_DPO` | Enable detail placement with improve_placement feature. |
| `DPO_MAX_DISPLACEMENT` | Specifies how far an instance can be moved when optimizing. |
| `GPL_TIMING_DRIVEN` | Specifies whether the placer should use timing driven placement. |
| `GPL_ROUTABILITY_DRIVEN` | Specifies whether the placer should use routability driven placement. |


### Clock Tree Synthesis(CTS)


| Variable | Description |
|----------------|---------------------------------------------------------------------------------------------------------------|
| `CTS_BUF_CELL` | The buffer cell used in the clock tree. |
| `FILL_CELLS` | Fill cells are used to fill empty sites. |
| Variable | Description |
|-----------------------|--------------------------------------------------------------------------------------------------------------|
| `CTS_BUF_CELL` | The buffer cell used in the clock tree. |
| `FILL_CELLS` | Fill cells are used to fill empty sites. |
| `SETUP_SLACK_MARGIN` | Specifies a time margin for the slack when fixing setup violations. |
| `HOLD_SLACK_MARGIN` | Specifies a time margin for the slack when fixing hold violations. This option allow you to overfix. |
| `FILL_CELLS` | Fill cells are used to fill empty sites. |


### Routing


| Variable | Description |
|---------------------|-----------------------------------------------------|
| `MIN_ROUTING_LAYER` | The lowest metal layer name to be used in routing. |
| `MAX_ROUTING_LAYER` | The highest metal layer name to be used in routing. |
| Variable | Description |
|-----------------------|-------------------------------------------------------------------------|
| `MIN_ROUTING_LAYER` | The lowest metal layer name to be used in routing. |
| `MAX_ROUTING_LAYER` | The highest metal layer name to be used in routing. |
| `DETAILED_ROUTE_ARGS` | Add additional arguments for debugging purpose during detail route. |
| `MACRO_EXTENSION` | Sets the number of GCells added to the blockages boundaries from macros.|


### Extraction
Expand All @@ -165,6 +187,7 @@ Note:
| `SET_RC_TCL` | Metal & Via RC definition file path. |
| `FILL_CONFIG` | JSON rule file for metal fill during chip finishing. |
| `KLAYOUT_TECH_FILE` | A mapping from LEF/DEF to GDS using the KLayout tool. |
| `IR_DROP_LAYER` | Default metal layer to report IR drop. |


## Design Specific Configuration Variables
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