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* added functionality for bitwise ops in evaluator * added tests for bitwise * pinned blueprint to correct commit
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Submodule blueprint
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12 files
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1 change: 0 additions & 1 deletion
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mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.json
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mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.res
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mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.json
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mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.res
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mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.json
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mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.res
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mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI16Simple.json
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[{"memref": {"data": [-23105, 19325, 20849, -30787, -28574, 6400, -17468, -25069, -3772, -5585], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [12315, -8527, -15259, -2999, 26965, -9250, -9078, 9823, -13382, -24594], "dims": [1, 10], "type": "int"}}] |
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mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI16Simple.onnx
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: | ||
in_a | ||
in_bout_a" | ||
BitwiseAndBitwiseAndI16SimpleZ | ||
in_a | ||
Z | ||
in_b | ||
b | ||
out_a | ||
B |
3 changes: 3 additions & 0 deletions
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mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI16Simple.res
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Result: | ||
memref<1x10xi16>[8219, 18993, 16481, -31735, 64, 6400, -26496, 1555, -16128, -30162] | ||
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mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI32Simple.json
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[{"memref": {"data": [-17405, -6334, 17342, -2390, 11827, -4355, 97, 24390, 5832, 21905], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [18283, 12705, -22076, 23371, -15509, -21397, 857, -24556, -30933, -31965], "dims": [1, 10], "type": "int"}}] |
4 changes: 2 additions & 2 deletions
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...omponent/BitwiseAnd/BitwiseAndSimple.onnx → .../Onnx/BitwiseAnd/BitwiseAndI32Simple.onnx
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@@ -1,8 +1,8 @@ | ||
:| | ||
: | ||
in_a | ||
in_bout_a" | ||
BitwiseAndBitwiseAndSimpleZ | ||
BitwiseAndBitwiseAndI32SimpleZ | ||
in_a | ||
|
3 changes: 3 additions & 0 deletions
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mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI32Simple.res
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Result: | ||
memref<1x10xi32>[1027, 8448, 388, 21002, 547, -21399, 65, 4, 1544, 257] | ||
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mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI64Simple.json
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[{"memref": {"data": [-31058, 24103, 20613, -14245, 30834, -9972, -16062, 24153, 6507, -2612], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [-5647, 8761, -16974, -18729, 26300, -32249, 2301, -19788, 27028, -9132], "dims": [1, 10], "type": "int"}}] |
20 changes: 20 additions & 0 deletions
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mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI64Simple.onnx
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,20 @@ | ||
: | ||
in_a | ||
in_bout_a" | ||
BitwiseAndBitwiseAndI64SimpleZ | ||
in_a | ||
Z | ||
in_b | ||
b | ||
out_a | ||
B |
3 changes: 3 additions & 0 deletions
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mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI64Simple.res
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@@ -0,0 +1,3 @@ | ||
Result: | ||
memref<1x10xi64>[-32608, 545, 4224, -32685, 24624, -32764, 64, 4624, 2304, -11196] | ||
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mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI8Simple.json
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[{"memref": {"data": [-99, 68, 14, -106, 31, 114, 45, 30, 35, 50], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [51, 77, 19, -123, 102, -44, -103, -7, 84, -105], "dims": [1, 10], "type": "int"}}] |
20 changes: 20 additions & 0 deletions
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mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI8Simple.onnx
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:~ | ||
in_a | ||
in_bout_a" | ||
BitwiseAndBitwiseAndI8SimpleZ | ||
in_a | ||
Z | ||
in_b | ||
b | ||
out_a | ||
B |
3 changes: 3 additions & 0 deletions
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mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI8Simple.res
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,3 @@ | ||
Result: | ||
memref<1x10xi8>[17, 68, 2, -124, 6, 80, 9, 24, 0, 18] | ||
22 |
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@@ -0,0 +1 @@ | ||
[{"memref": {"data": [-23105, 19325, 20849, -30787, -28574, 6400, -17468, -25069, -3772, -5585], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [12315, -8527, -15259, -2999, 26965, -9250, -9078, 9823, -13382, -24594], "dims": [1, 10], "type": "int"}}] |
19 changes: 19 additions & 0 deletions
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mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI16Simple.onnx
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,19 @@ | ||
:} | ||
in_a | ||
in_bout_a" BitwiseOrBitwiseOrI16SimpleZ | ||
in_a | ||
Z | ||
in_b | ||
b | ||
out_a | ||
B |
3 changes: 3 additions & 0 deletions
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mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI16Simple.res
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,3 @@ | ||
Result: | ||
memref<1x10xi16>[-19009, -8195, -10891, -2051, -1673, -9250, -50, -16801, -1026, -17] | ||
22 |
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