Routine commit

canal/cyclone.py

@@ -328,7 +328,10 @@ def __eq__(self, other):
         return True
 
     def __repr__(self):
-        return f"SWITCH {self.width} {self.id} {self.num_track}"
+        if self.isTall:
+            return f"TALLSWITCH {self.width} {self.id} {self.num_track} {self.num_horizontal_track}"
+        else:
+            return f"SWITCH {self.width} {self.id} {self.num_track}"
 
     def __getitem__(self, item: Tuple[SwitchBoxSide, int, SwitchBoxIO]):
         if not isinstance(item, tuple):
@@ -706,6 +709,7 @@ def __init__(self, x: int, y: int,
         self.y = y
         self.track_width = track_width
         self.height = height
+        self.isTallTile = isTallTile
 
         # create a copy of switch box because the switchbox nodes have to be
         # created
@@ -961,12 +965,13 @@ def set_core_connection(self, x: int, y: int, port_name: str,
 
     def set_core_connection_all(self, port_name: str,
                                 connection_type: List[Tuple[SwitchBoxSide,
-                                                            SwitchBoxIO]], includeTallConnections: bool = False):
+                                                            SwitchBoxIO]]):
         """helper function to set connections for all the tiles with the
         same port_name"""
         for (x, y), tile in self.__tiles.items():
             # construct the connection types
             switch = tile.switchbox
+            includeTallConnections = tile.isTallTile
             num_track = switch.num_track
             connections: List[SBConnectionType] = []
             for side, io in connection_type:

canal/util.py

@@ -201,13 +201,8 @@ def create_uniform_interconnect(width: int,
     port_names.sort()
     for port_name in port_names:
         conns = port_connections[port_name]
+        interconnect.set_core_connection_all(port_name, conns)
 
-        # MO: TALL SB HACK
-        # TODO: Add AND include_tall here 
-        if "f2io" in port_name or "io2f" in port_name:
-            interconnect.set_core_connection_all(port_name, conns, includeTallConnections=True)
-        else:
-            interconnect.set_core_connection_all(port_name, conns)
 
     if inter_core_connection is not None:
         interconnect.set_inter_core_connection(inter_core_connection)
@@ -253,13 +248,20 @@ def create_uniform_interconnect(width: int,
     # insert pipeline register
     if pipeline_reg is None:
         pipeline_reg = []
-    for track, side in pipeline_reg:
-        for coord in interconnect:
-            tile = interconnect[coord]
+    for coord in interconnect:
+        tile = interconnect[coord]
+
+        pipeline_regs_to_add = pipeline_reg.copy()
+        if tile.isTallTile:
+            for track in range(tile.switchbox.num_track, tile.switchbox.num_horizontal_track):
+                pipeline_regs_to_add.append((track, SwitchBoxSide.WEST))
+                pipeline_regs_to_add.append((track, SwitchBoxSide.EAST))
+
+        for track, side in pipeline_regs_to_add:
             if tile.switchbox is None or tile.switchbox.num_track == 0:
                 continue
-            if track < tile.switchbox.num_track:
-                tile.switchbox.add_pipeline_register(side, track)
+            # if track < num_tracks_to_loop_over:
+            tile.switchbox.add_pipeline_register(side, track)
 
     return interconnect