Merge pull request #62 from StanfordAHA/hetero-cgra

Matrix unit I/O tiles

canal/cyclone.py

@@ -494,6 +494,7 @@ def __add_core(self, core: InterconnectCore,
                     self.__port_core[port_name].append(core)
 
         if connection_type & CoreConnectionType.SB == CoreConnectionType.SB:
+
             outputs = core.outputs()[:]
             outputs.sort(key=lambda x: x[1])
             for width, port_name in outputs:

canal/global_signal.py

@@ -9,6 +9,7 @@
 from gemstone.common.configurable import ConfigurationType
 from .interconnect import Interconnect
 from .util import IOSide, get_array_size
+from typing import Tuple, Dict, List, Tuple
 
 
 @enum.unique
@@ -34,7 +35,7 @@ def get_x_range_cores(interconnect: Interconnect):
     return x_min, x_max
 
 
-def apply_global_fanout_wiring(interconnect: Interconnect, io_sides: IOSide = IOSide.None_):
+def apply_global_fanout_wiring(interconnect: Interconnect, io_sides: List[IOSide] = [IOSide.None_]):
     # straight-forward fanout for global signals
     x_min, x_max, = get_x_range_cores(interconnect)
     global_ports = interconnect.globals
@@ -72,7 +73,7 @@ def apply_global_fanout_wiring(interconnect: Interconnect, io_sides: IOSide = IO
     return interconnect_read_data_or
 
 
-def apply_global_meso_wiring(interconnect: Interconnect, io_sides: IOSide = IOSide.None_):
+def apply_global_meso_wiring(interconnect: Interconnect, io_sides: List[IOSide] = [IOSide.None_]):
     # "river routing" for global signal
     global_ports = interconnect.globals
     x_min, x_max, = get_x_range_cores(interconnect)
@@ -145,7 +146,7 @@ def apply_global_meso_wiring(interconnect: Interconnect, io_sides: IOSide = IOSi
 
 
 def apply_global_parallel_meso_wiring(interconnect: Interconnect,
-                                      io_sides: IOSide = IOSide.None_, num_cfg: int = 1):
+                                      io_sides: List[IOSide] = [IOSide.None_], num_cfg: int = 1):
 
     interconnect_read_data_or = apply_global_meso_wiring(interconnect)
     # interconnect must have config port

canal/interconnect.py

@@ -697,6 +697,8 @@ def parse_node(self, node_str):
         elif node_str[0] == "REG":
             reg_name, track, x, y, bit_width = node_str[1:]
             graph = self.get_graph(bit_width)
+            if reg_name not in graph.get_tile(x, y).switchbox.registers:
+                breakpoint()
             return graph.get_tile(x, y).switchbox.registers[reg_name]
         elif node_str[0] == "RMUX":
             rmux_name, x, y, bit_width = node_str[1:]

canal/util.py

@@ -37,10 +37,10 @@ def compute_num_tracks(x_offset: int, y_offset: int,
 
 
 def get_array_size(width, height, io_sides):
-    x_min = 1 if io_sides & IOSide.West else 0
-    x_max = width - 2 if io_sides & IOSide.East else width - 1
-    y_min = 1 if io_sides & IOSide.North else 0
-    y_max = height - 2 if io_sides & IOSide.South else height - 1
+    x_min = 1 if IOSide.West in io_sides else 0
+    x_max = width - 2 if IOSide.East in io_sides else width - 1
+    y_min = 1 if IOSide.North in io_sides else 0
+    y_max = height - 2 if IOSide.South in io_sides else height - 1
     return x_min, x_max, y_min, y_max
 
 
@@ -56,7 +56,7 @@ def create_uniform_interconnect(width: int,
                                 sb_type: SwitchBoxType,
                                 pipeline_reg:
                                 List[Tuple[int, SwitchBoxSide]] = None,
-                                io_sides: IOSide = IOSide.None_,
+                                io_sides: List[IOSide] = [IOSide.None_],
                                 io_conn: Dict[str, Dict[str, List[int]]] = None,
                                 additional_core_fn: Callable[[int, int], Core] = lambda _, __: None,
                                 inter_core_connection: Dict[str, List[str]] = None
@@ -87,14 +87,14 @@ def create_uniform_interconnect(width: int,
 
     :return configured Interconnect object
     """
-    if io_sides & IOSide.None_ or io_conn is None:
+    if IOSide.None_ in io_sides or io_conn is None:
         io_conn = {"in": {}, "out": {}}
     tile_height = 1
     interconnect = InterconnectGraph(track_width)
     # based on the IO sides specified. these are inclusive
     # once it's assigned to None, nullify everything
-    if io_sides & IOSide.None_:
-        io_sides = IOSide.None_
+    if IOSide.None_ in io_sides:
+        io_sides = [IOSide.None_]
     x_min, x_max, y_min, y_max = get_array_size(width, height, io_sides)
     # create tiles and set cores
     for x in range(x_min, x_max + 1):
@@ -115,6 +115,7 @@ def create_uniform_interconnect(width: int,
 
             interconnect.add_tile(tile_circuit)
             core = column_core_fn(x, y)
+
             core_interface = CoreInterface(core)
             interconnect.set_core(x, y, core_interface)
 
@@ -132,11 +133,13 @@ def create_uniform_interconnect(width: int,
             if tile is not None:
                 continue
             core = column_core_fn(x, y)
+
             sb = SwitchBox(x, y, 0, track_width, [])
             tile_circuit = Tile(x, y, track_width, sb, tile_height)
-            interconnect.add_tile(tile_circuit)
+            interconnect.add_tile(tile_circuit)   
             core_interface = CoreInterface(core)
             interconnect.set_core(x, y, core_interface)
+
 
     # set port connections
     port_names = list(port_connections.keys())
@@ -182,9 +185,9 @@ def create_uniform_interconnect(width: int,
 def connect_io(interconnect: InterconnectGraph,
                input_port_conn: Dict[str, List[int]],
                output_port_conn: Dict[str, List[int]],
-               io_sides: IOSide):
+               io_sides: List[IOSide]):
     """connect tiles on the side"""
-    if io_sides & IOSide.None_:
+    if IOSide.None_ in io_sides:
         return
 
     width, height = interconnect.get_size()
@@ -195,8 +198,10 @@ def connect_io(interconnect: InterconnectGraph,
             if x in range(x_min, x_max + 1) and \
                     y in range(y_min, y_max + 1):
                 continue
+
             # make sure that these margins tiles have empty switch boxes
             tile = interconnect[(x, y)]
+
             if tile.core.core is None:
                 continue
             assert tile.switchbox.num_track == 0
@@ -215,6 +220,7 @@ def connect_io(interconnect: InterconnectGraph,
                 next_tile = interconnect[(x, y - 1)]
                 side = SwitchBoxSide.SOUTH
             for input_port, conn in input_port_conn.items():
+                #breakpoint()
                 # input is from fabric to IO
                 if input_port in tile.ports:
                     port_node = tile.ports[input_port]
@@ -226,6 +232,8 @@ def connect_io(interconnect: InterconnectGraph,
                             sb_node = next_tile.get_sb(side, track,
                                                        SwitchBoxIO.SB_OUT)
                             sb_node.add_edge(port_node)
+
+
             for output_port, conn in output_port_conn.items():
                 # output is IO to fabric
                 if output_port in tile.ports: