Version 4.4.0 of the Gecko SDK

.properties

@@ -1,9 +1,14 @@
 id=com.silabs.sdk.exx32
-version=4.3.0
+version=4.4.0
 label=Gecko SDK
 description=Silicon Labs Gecko SDK
 supportedParts=mcu.arm.efm32.g\..* mcu.arm.efm32.gg.* mcu.arm.efm32.hg.* mcu.arm.efm32.jg.* mcu.arm.efm32.lg.* mcu.arm.efm32.pg.* mcu.arm.efm32.tg.* mcu.arm.efm32.wg.* mcu.arm.efm32.zg.* mcu.arm.ezr32.lg.* mcu.arm.ezr32.wg.* mcu.arm.ezr32.hg.*
 prop.file.templatesFile=.studio/builtinTemplates.xml .studio/templates.xml
 prop.file.demosFile=.studio/demos.xml
 prop.file.modulesFile=.studio/modules.xml
 prop.file.appnotesFile=.studio/appnotes.xml
+
+
+# General properties are prepended with "prop."
+prop.file.gccLinkerScript=.studio/linkerScripts/linker_script_efm32_v4.ld
+prop.docURL=http://devtools.silabs.com/dl/documentation/doxygen/4.4.0/index.html

Device/Changes-Device.txt

@@ -1,5 +1,18 @@
 ================ Revision history ============================================
+4.4.0:
+ - Added support for sub GHz EFR devices.
+ - Added support for BGM121 (EFR32BG1X232FXXXGM56) module.
+ - Fixed bug in USB_GRXSTSR_FN on Giant/Leopard/Wonder families.
+   The bit field was not correctly placed in the register.
+
+4.3.1:
+ - The "SECURITY" Peripheral Register Block has been renamed to "AESCCM" to
+   avoid naming collisions.
+ - If the name MPU_BASE is already defined, it is undefined in the Device
+   header such that the CMSIS Core definitions can be used.
+
 4.3.0:
+ - Use ARM CMSIS version 4.5.0.
  - Renamed some bitfields in ADC for Pearl/Jade/EFR's.
  - Added usb LEMNAK and LEMADDR low power modes on Happy Gecko devices.
  - SystemHFClockGet() is now calculating the frequency taking the HFCLK or
@@ -18,7 +31,7 @@
 
 4.1.0:
  - Added device headers for new families EZR32HG (EZR Happy Gecko), EFM32JG
-   (Jade Gecko) and EFM32PG (Pearl Gecko)
+   (Jade Gecko) and EFM32PG (Pearl Gecko).
  - Bugfixes in EZR32 LG and WG system/startup files.
  - Added support for new EZR32HG family.
 

Device/SiliconLabs/EFM32G/Include/efm32g200f16.h

@@ -2,7 +2,7 @@
  * @file efm32g200f16.h
  * @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
  *        for EFM EFM32G200F16
- * @version 4.3.0
+ * @version 4.4.0
  ******************************************************************************
  * @section License
  * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
@@ -235,34 +235,34 @@ typedef enum IRQn
  *****************************************************************************/
 typedef struct
 {
-  __I uint32_t   STATUS;         /**< DMA Status Registers  */
-  __O uint32_t   CONFIG;         /**< DMA Configuration Register  */
-  __IO uint32_t  CTRLBASE;       /**< Channel Control Data Base Pointer Register  */
-  __I uint32_t   ALTCTRLBASE;    /**< Channel Alternate Control Data Base Pointer Register  */
-  __I uint32_t   CHWAITSTATUS;   /**< Channel Wait on Request Status Register  */
-  __O uint32_t   CHSWREQ;        /**< Channel Software Request Register  */
-  __IO uint32_t  CHUSEBURSTS;    /**< Channel Useburst Set Register  */
-  __O uint32_t   CHUSEBURSTC;    /**< Channel Useburst Clear Register  */
-  __IO uint32_t  CHREQMASKS;     /**< Channel Request Mask Set Register  */
-  __O uint32_t   CHREQMASKC;     /**< Channel Request Mask Clear Register  */
-  __IO uint32_t  CHENS;          /**< Channel Enable Set Register  */
-  __O uint32_t   CHENC;          /**< Channel Enable Clear Register  */
-  __IO uint32_t  CHALTS;         /**< Channel Alternate Set Register  */
-  __O uint32_t   CHALTC;         /**< Channel Alternate Clear Register  */
-  __IO uint32_t  CHPRIS;         /**< Channel Priority Set Register  */
-  __O uint32_t   CHPRIC;         /**< Channel Priority Clear Register  */
+  __IM uint32_t  STATUS;         /**< DMA Status Registers  */
+  __OM uint32_t  CONFIG;         /**< DMA Configuration Register  */
+  __IOM uint32_t CTRLBASE;       /**< Channel Control Data Base Pointer Register  */
+  __IM uint32_t  ALTCTRLBASE;    /**< Channel Alternate Control Data Base Pointer Register  */
+  __IM uint32_t  CHWAITSTATUS;   /**< Channel Wait on Request Status Register  */
+  __OM uint32_t  CHSWREQ;        /**< Channel Software Request Register  */
+  __IOM uint32_t CHUSEBURSTS;    /**< Channel Useburst Set Register  */
+  __OM uint32_t  CHUSEBURSTC;    /**< Channel Useburst Clear Register  */
+  __IOM uint32_t CHREQMASKS;     /**< Channel Request Mask Set Register  */
+  __OM uint32_t  CHREQMASKC;     /**< Channel Request Mask Clear Register  */
+  __IOM uint32_t CHENS;          /**< Channel Enable Set Register  */
+  __OM uint32_t  CHENC;          /**< Channel Enable Clear Register  */
+  __IOM uint32_t CHALTS;         /**< Channel Alternate Set Register  */
+  __OM uint32_t  CHALTC;         /**< Channel Alternate Clear Register  */
+  __IOM uint32_t CHPRIS;         /**< Channel Priority Set Register  */
+  __OM uint32_t  CHPRIC;         /**< Channel Priority Clear Register  */
   uint32_t       RESERVED0[3];   /**< Reserved for future use **/
-  __IO uint32_t  ERRORC;         /**< Bus Error Clear Register  */
+  __IOM uint32_t ERRORC;         /**< Bus Error Clear Register  */
   uint32_t       RESERVED1[880]; /**< Reserved for future use **/
-  __I uint32_t   CHREQSTATUS;    /**< Channel Request Status  */
+  __IM uint32_t  CHREQSTATUS;    /**< Channel Request Status  */
   uint32_t       RESERVED2[1];   /**< Reserved for future use **/
-  __I uint32_t   CHSREQSTATUS;   /**< Channel Single Request Status  */
+  __IM uint32_t  CHSREQSTATUS;   /**< Channel Single Request Status  */
 
   uint32_t       RESERVED3[121]; /**< Reserved for future use **/
-  __I uint32_t   IF;             /**< Interrupt Flag Register  */
-  __IO uint32_t  IFS;            /**< Interrupt Flag Set Register  */
-  __IO uint32_t  IFC;            /**< Interrupt Flag Clear Register  */
-  __IO uint32_t  IEN;            /**< Interrupt Enable register  */
+  __IM uint32_t  IF;             /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS;            /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC;            /**< Interrupt Flag Clear Register  */
+  __IOM uint32_t IEN;            /**< Interrupt Enable register  */
 
   uint32_t       RESERVED4[60];  /**< Reserved registers */
 
@@ -280,40 +280,40 @@ typedef struct
  *****************************************************************************/
 typedef struct
 {
-  __IO uint32_t CTRL;         /**< CMU Control Register  */
-  __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register  */
-  __IO uint32_t HFPERCLKDIV;  /**< High Frequency Peripheral Clock Division Register  */
-  __IO uint32_t HFRCOCTRL;    /**< HFRCO Control Register  */
-  __IO uint32_t LFRCOCTRL;    /**< LFRCO Control Register  */
-  __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register  */
-  __IO uint32_t CALCTRL;      /**< Calibration Control Register  */
-  __IO uint32_t CALCNT;       /**< Calibration Counter Register  */
-  __IO uint32_t OSCENCMD;     /**< Oscillator Enable/Disable Command Register  */
-  __IO uint32_t CMD;          /**< Command Register  */
-  __IO uint32_t LFCLKSEL;     /**< Low Frequency Clock Select Register  */
-  __I uint32_t  STATUS;       /**< Status Register  */
-  __I uint32_t  IF;           /**< Interrupt Flag Register  */
-  __IO uint32_t IFS;          /**< Interrupt Flag Set Register  */
-  __IO uint32_t IFC;          /**< Interrupt Flag Clear Register  */
-  __IO uint32_t IEN;          /**< Interrupt Enable Register  */
-  __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0  */
-  __IO uint32_t HFPERCLKEN0;  /**< High Frequency Peripheral Clock Enable Register 0  */
-  uint32_t      RESERVED0[2]; /**< Reserved for future use **/
-  __I uint32_t  SYNCBUSY;     /**< Synchronization Busy Register  */
-  __IO uint32_t FREEZE;       /**< Freeze Register  */
-  __IO uint32_t LFACLKEN0;    /**< Low Frequency A Clock Enable Register 0  (Async Reg)  */
-  uint32_t      RESERVED1[1]; /**< Reserved for future use **/
-  __IO uint32_t LFBCLKEN0;    /**< Low Frequency B Clock Enable Register 0 (Async Reg)  */
-  uint32_t      RESERVED2[1]; /**< Reserved for future use **/
-  __IO uint32_t LFAPRESC0;    /**< Low Frequency A Prescaler Register 0 (Async Reg)  */
-  uint32_t      RESERVED3[1]; /**< Reserved for future use **/
-  __IO uint32_t LFBPRESC0;    /**< Low Frequency B Prescaler Register 0  (Async Reg)  */
-  uint32_t      RESERVED4[1]; /**< Reserved for future use **/
-  __IO uint32_t PCNTCTRL;     /**< PCNT Control Register  */
-  uint32_t      RESERVED5[1]; /**< Reserved for future use **/
-  __IO uint32_t ROUTE;        /**< I/O Routing Register  */
-  __IO uint32_t LOCK;         /**< Configuration Lock Register  */
-} CMU_TypeDef;                /** @} */
+  __IOM uint32_t CTRL;         /**< CMU Control Register  */
+  __IOM uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register  */
+  __IOM uint32_t HFPERCLKDIV;  /**< High Frequency Peripheral Clock Division Register  */
+  __IOM uint32_t HFRCOCTRL;    /**< HFRCO Control Register  */
+  __IOM uint32_t LFRCOCTRL;    /**< LFRCO Control Register  */
+  __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register  */
+  __IOM uint32_t CALCTRL;      /**< Calibration Control Register  */
+  __IOM uint32_t CALCNT;       /**< Calibration Counter Register  */
+  __IOM uint32_t OSCENCMD;     /**< Oscillator Enable/Disable Command Register  */
+  __IOM uint32_t CMD;          /**< Command Register  */
+  __IOM uint32_t LFCLKSEL;     /**< Low Frequency Clock Select Register  */
+  __IM uint32_t  STATUS;       /**< Status Register  */
+  __IM uint32_t  IF;           /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS;          /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC;          /**< Interrupt Flag Clear Register  */
+  __IOM uint32_t IEN;          /**< Interrupt Enable Register  */
+  __IOM uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0  */
+  __IOM uint32_t HFPERCLKEN0;  /**< High Frequency Peripheral Clock Enable Register 0  */
+  uint32_t       RESERVED0[2]; /**< Reserved for future use **/
+  __IM uint32_t  SYNCBUSY;     /**< Synchronization Busy Register  */
+  __IOM uint32_t FREEZE;       /**< Freeze Register  */
+  __IOM uint32_t LFACLKEN0;    /**< Low Frequency A Clock Enable Register 0  (Async Reg)  */
+  uint32_t       RESERVED1[1]; /**< Reserved for future use **/
+  __IOM uint32_t LFBCLKEN0;    /**< Low Frequency B Clock Enable Register 0 (Async Reg)  */
+  uint32_t       RESERVED2[1]; /**< Reserved for future use **/
+  __IOM uint32_t LFAPRESC0;    /**< Low Frequency A Prescaler Register 0 (Async Reg)  */
+  uint32_t       RESERVED3[1]; /**< Reserved for future use **/
+  __IOM uint32_t LFBPRESC0;    /**< Low Frequency B Prescaler Register 0  (Async Reg)  */
+  uint32_t       RESERVED4[1]; /**< Reserved for future use **/
+  __IOM uint32_t PCNTCTRL;     /**< PCNT Control Register  */
+  uint32_t       RESERVED5[1]; /**< Reserved for future use **/
+  __IOM uint32_t ROUTE;        /**< I/O Routing Register  */
+  __IOM uint32_t LOCK;         /**< Configuration Lock Register  */
+} CMU_TypeDef;                 /** @} */
 
 #include "efm32g_timer_cc.h"
 #include "efm32g_timer.h"
@@ -332,8 +332,8 @@ typedef struct
  *****************************************************************************/
 typedef struct
 {
-  __IO uint32_t  SWPULSE;      /**< Software Pulse Register  */
-  __IO uint32_t  SWLEVEL;      /**< Software Level Register  */
+  __IOM uint32_t SWPULSE;      /**< Software Pulse Register  */
+  __IOM uint32_t SWLEVEL;      /**< Software Level Register  */
 
   uint32_t       RESERVED0[2]; /**< Reserved registers */