part1.qsf.bak

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#
# Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
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# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
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# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version
# Date created = 10:11:02  October 01, 2010
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		part1_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY part1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:11:02  OCTOBER 01, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name VERILOG_FILE Altera_UP_Audio_Bit_Counter.v
set_global_assignment -name VERILOG_FILE Altera_UP_Audio_In_Deserializer.v
set_global_assignment -name VERILOG_FILE Altera_UP_Audio_Out_Serializer.v
set_global_assignment -name VERILOG_FILE Altera_UP_Clock_Edge.v
set_global_assignment -name VERILOG_FILE Altera_UP_I2C.v
set_global_assignment -name VERILOG_FILE Altera_UP_I2C_AV_Auto_Initialize.v
set_global_assignment -name VERILOG_FILE Altera_UP_I2C_DC_Auto_Initialize.v
set_global_assignment -name VERILOG_FILE Altera_UP_I2C_LCM_Auto_Initialize.v
set_global_assignment -name VERILOG_FILE Altera_UP_Slow_Clock_Generator.v
set_global_assignment -name VERILOG_FILE Altera_UP_SYNC_FIFO.v
set_global_assignment -name VERILOG_FILE audio_and_video_config.v
set_global_assignment -name VERILOG_FILE audio_codec.v
set_global_assignment -name VERILOG_FILE clock_generator.v
set_global_assignment -name VHDL_FILE part1.vhd
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 780
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top