Skip to content

Commit

Permalink
Adjust ram sections
Browse files Browse the repository at this point in the history
  • Loading branch information
Ralim committed Mar 26, 2023
1 parent 4999632 commit 11d6622
Showing 1 changed file with 4 additions and 4 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -17,16 +17,16 @@ OUTPUT_ARCH( "riscv" )
/* configure the entry point */
ENTRY(_enter)

StackSize = 0x1000; /* 4KB */
HeapSize = 0x1000; /* 4KB */
StackSize = 0x800; /* 2KB */
HeapSize = 0x800; /* 2KB */
__EM_SIZE = DEFINED(ble_controller_init) ? 8K : 0K;

MEMORY
{
xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1022K
itcm_memory (rx) : ORIGIN = 0x22014000, LENGTH = 16K
dtcm_memory (rx) : ORIGIN = 0x42018000, LENGTH = 32K
ram_memory (!rx) : ORIGIN = 0x42020000, LENGTH = 32K
dtcm_memory (rx) : ORIGIN = 0x42017000, LENGTH = 4K
ram_memory (!rx) : ORIGIN = 0x42018000, LENGTH = 64K
rsvd_memory (!rx) : ORIGIN = 0x42028000, LENGTH = 1K
ram2_memory (!rx) : ORIGIN = 0x42028400, LENGTH = (31K - __EM_SIZE)
hbn_memory (rx) : ORIGIN = 0x40010000, LENGTH = 0xE00 /* hbn ram 4K used 3.5K*/
Expand Down

0 comments on commit 11d6622

Please sign in to comment.