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[NHWC][asm igemm] add support for several NHWC bwd ssd config, when k=4x, 2x #1114

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merged 3 commits into from
Sep 1, 2021

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carlushuang
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@carlushuang carlushuang commented Aug 25, 2021

convfp16 -n 120 -c 256 -H 1 -W 1 -k 340 -y 3 -x 3 -p 1 -q 1 -u 1 -v 1 -l 1 -j 1 -m conv -g 1 -F 2 -t 1 --in_layout NHWC --fil_layout NHWC --out_layout NHWC
convfp16 -n 120 -c 256 -H 3 -W 3 -k 340 -y 3 -x 3 -p 1 -q 1 -u 1 -v 1 -l 1 -j 1 -m conv -g 1 -F 2 -t 1 --in_layout NHWC --fil_layout NHWC --out_layout NHWC
convfp16 -n 120 -c 256 -H 5 -W 5 -k 510 -y 3 -x 3 -p 1 -q 1 -u 1 -v 1 -l 1 -j 1 -m conv -g 1 -F 2 -t 1 --in_layout NHWC --fil_layout NHWC --out_layout NHWC
convfp16 -n 120 -c 512 -H 10 -W 10 -k 510 -y 3 -x 3 -p 1 -q 1 -u 1 -v 1 -l 1 -j 1 -m conv -g 1 -F 2 -t 1 --in_layout NHWC --fil_layout NHWC --out_layout NHWC
convfp16 -n 120 -c 512 -H 19 -W 19 -k 510 -y 3 -x 3 -p 1 -q 1 -u 1 -v 1 -l 1 -j 1 -m conv -g 1 -F 2 -t 1 --in_layout NHWC --fil_layout NHWC --out_layout NHWC
convfp16 -n 120 -c 256 -H 38 -W 38 -k 340 -y 3 -x 3 -p 1 -q 1 -u 1 -v 1 -l 1 -j 1 -m conv -g 1 -F 2 -t 1 --in_layout NHWC --fil_layout NHWC --out_layout NHWC

SSD configs of above are currently not supported in MIOpen. This PR add support for these configs by adding several new kernels which support padded gemm k.

This PR has only 1 .cpp file and 1 .txt file changed, other is asm files. Need feedback of #1113 first then consider if continue integrate asm file as plain text or in other form like .tar.bz2 keep current process as discussed in #1113 (comment)

perf data : ssd-perf, please check tab PR1114

@codecov

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@carlushuang carlushuang requested a review from junliume August 25, 2021 12:41
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LGTM
Just please push a performance data for the aimed cases.

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@shaojiewang OK, updated in description.

@carlushuang carlushuang requested a review from junliume September 1, 2021 07:09
@junliume junliume merged commit fc65456 into develop Sep 1, 2021
@carlushuang carlushuang deleted the asm_igemm_bwd_nhwc_add_support_padded_k branch September 2, 2021 04:07
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atamazov commented Sep 2, 2021

@carlushuang Does it require retuning? Which solvers? What may happen until retuning is done?

/cc @JehandadKhan

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carlushuang commented Sep 4, 2021

@atamazov sorry for missing information here. Yes, this PR may affect ConvAsmImplicitGemmGTCDynamicBwdXdlopsNHWC. Before this PR, this solver just not support the config where k=4x or 2x. After this PR, now it can support. The real convolution configs affected is listed in description of this PR, the SSD configs.

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4 participants