fixup! cpu/efm32: efr32mg12p: update vendor headers per #8873.

RIOT-OS · Apr 4, 2018 · e53967d · e53967d
1 parent 8a45d98
commit e53967d
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Showing 51 changed files with 574 additions and 545 deletions.
diff --git a/cpu/efm32/families/efr32mg12p/cpus.txt b/cpu/efm32/families/efr32mg12p/cpus.txt
@@ -9,16 +9,23 @@
 efr32mg12p432f1024gm68 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00040000 1 1 1
 efr32mg12p332f1024im48 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00040000 1 1 1
 efr32mg12p432f1024im48 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00040000 1 1 1
+efr32mg12p231f1024gm48 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00020000 1 1 1
 efr32mg12p432f1024gl125 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00040000 1 1 1
+efr32mg12p232f512gm68 efr32mg12p 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00010000 1 1 1
 efr32mg12p332f1024gl125 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00040000 1 1 1
+efr32mg12p232f1024gm68 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00020000 1 1 1
 efr32mg12p132f1024gm48 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00020000 1 1 1
+efr32mg12p431f1024gm48 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00040000 1 1 1
 efr32mg12p433f1024il125 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00040000 1 1 1
+efr32mg12p132f512gm68 efr32mg12p 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00010000 1 1 1
 efr32mg12p433f1024gm48 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00040000 1 1 1
 efr32mg12p433f1024gm68 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00040000 1 1 1
 efr32mg12p433f1024gl125 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00040000 1 1 1
 efr32mg12p433f1024im48 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00040000 1 1 1
+efr32mg12p231f1024gm68 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00020000 1 1 1
 efr32mg12p232f1024gl125 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00020000 1 1 1
 efr32mg12p432f1024gm48 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00040000 1 1 1
 efr32mg12p332f1024gm48 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00040000 1 1 1
+efr32mg12p431f1024gm68 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00040000 1 1 1
 efr32mg12p132f1024gl125 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00020000 1 1 1
 efr32mg12p232f1024gm48 efr32mg12p 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00020000 1 1 1
diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p332f1024gl125.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p332f1024gl125.h
@@ -2,10 +2,10 @@
  * @file efr32mg12p332f1024gl125.h
  * @brief CMSIS Cortex-M Peripheral Access Layer Header File
  *        for EFR32MG12P332F1024GL125
- * @version 5.3.3
+ * @version 5.4.0
  ******************************************************************************
  * # License
- * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2017 Silicon Laboratories, Inc. www.silabs.com</b>
  ******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -251,11 +251,11 @@ typedef enum IRQn{
 #define EXT_IRQ_COUNT              51             /**< Number of External (NVIC) interrupts */
 
 /** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX                 136
+#define AFCHAN_MAX                 136U
 /** AF channel maximum location number */
-#define AFCHANLOC_MAX              32
+#define AFCHANLOC_MAX              32U
 /** Analog AF channels */
-#define AFACHAN_MAX                125
+#define AFACHAN_MAX                125U
 
 /* Part number capabilities */
 
@@ -633,7 +633,7 @@ typedef enum IRQn{
 #define _WTIMER_CTRL_ATI_MASK                       0x10000000UL                              /**< Bit mask for TIMER_ATI */
 #define _WTIMER_CTRL_ATI_DEFAULT                    0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
 #define WTIMER_CTRL_ATI_DEFAULT                     (_WTIMER_CTRL_ATI_DEFAULT << 28)          /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RSSCOIST                        (0x1UL << 29)                             /**< Reload-Start Sets Compare Output initial State */
+#define WTIMER_CTRL_RSSCOIST                        (0x1UL << 29)                             /**< Reload-Start Sets Compare Output Initial State */
 #define _WTIMER_CTRL_RSSCOIST_SHIFT                 29                                        /**< Shift value for TIMER_RSSCOIST */
 #define _WTIMER_CTRL_RSSCOIST_MASK                  0x20000000UL                              /**< Bit mask for TIMER_RSSCOIST */
 #define _WTIMER_CTRL_RSSCOIST_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1738,7 +1738,7 @@ typedef enum IRQn{
 #define _WTIMER_DTCTRL_DTIPOL_MASK                  0x4UL                                  /**< Bit mask for TIMER_DTIPOL */
 #define _WTIMER_DTCTRL_DTIPOL_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for WTIMER_DTCTRL */
 #define WTIMER_DTCTRL_DTIPOL_DEFAULT                (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2)   /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTCINV                        (0x1UL << 3)                           /**< DTI Complementary Output Invert. */
+#define WTIMER_DTCTRL_DTCINV                        (0x1UL << 3)                           /**< DTI Complementary Output Invert */
 #define _WTIMER_DTCTRL_DTCINV_SHIFT                 3                                      /**< Shift value for TIMER_DTCINV */
 #define _WTIMER_DTCTRL_DTCINV_MASK                  0x8UL                                  /**< Bit mask for TIMER_DTCINV */
 #define _WTIMER_DTCTRL_DTCINV_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for WTIMER_DTCTRL */