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Classical condition boxes are now drawn as bullets in text drawer #6370
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Hey @1ucian0 . I was actually unable to give the condition value as '0x2' as that would require a significant amount of code change. However, in the new circuit diagram the condition values are given as '=2'. I suppose that is fine. |
@TharrmashasthaPV #5938 fixes a problem with condition bits not reordering when
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Dont forget the reno!
Sorry @enavarro51 . I missed your comment somehow. Sure, I will fix that. Just to keep things a bit simple, I will push that as a different PR. Thanks a lot for pointing this out!!! |
Let me know when you add the @enavarro51 fix . Once done, I think it will be ready to go. |
Co-authored-by: Edwin Navarro <[email protected]>
Hi @1ucian0 . I have added the fix for the |
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Thanks Tharrma!
I had to push a new commit since there were some conflicts with main. I have resolved the conflicts. The changes were minor. I guess this PR needs a re-review. Sorry for the inconvenience. |
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This LGTM 🚀 @1ucian0 thoughts?
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Thanks!
…onditioning (#6261) * Cbit conditional * lint fixed * q * added_tests * Added tests * lint fix * lint-fix * added extra test * unwanted comment removed * refactored for bit.register deprication * text drawer support for single bit cond * resolved conflicts * Added reno * Update utils.py * Removing redundant structures * lint fix * blacking and linting * Black fix * Corrected tests compression and refactored for #6370 Co-authored-by: Thomas Alexander <[email protected]> Co-authored-by: Luciano Bello <[email protected]> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Summary
Fixes #6290 .
Details and comments
In this PR, the classical condition boxes are replaced with open and close bullets when cregbundle=False. This ensures that the text drawer drawings of classical conditioned gates are consistent with that of the latex and mpl drawers.
For instance, the example circuit given in #6290 is now drawn as
Update:
As it was suggested in the comment, the conditional value is also drawn along with the circuit. It looks like the following
Also the existing tests have been modified and new tests have been added.