Text drawer extended for drawing circuits with single classical bit conditioning

qiskit/dagcircuit/dagcircuit.py

@@ -600,20 +600,19 @@ def _map_condition(wire_map, condition, target_cregs):
                         )
                     except StopIteration as ex:
                         raise DAGCircuitError(
-                            "Did not find creg containing " "mapped clbit in conditional."
+                            "Did not find creg containing mapped clbit in conditional."
                         ) from ex
                 else:
                     # If cond is on a single Clbit then the candidate_creg is
                     # the target Clbit to which 'bit' is mapped to.
                     candidate_creg = wire_map[bit]
-
                 if new_creg is None:
                     new_creg = candidate_creg
                 elif new_creg != candidate_creg:
                     # Raise if wire_map maps condition creg on to more than one
                     # creg in target DAG.
                     raise DAGCircuitError(
-                        "wire_map maps conditional " "register onto more than one creg."
+                        "wire_map maps conditional register onto more than one creg."
                     )
 
                 if not is_reg:

qiskit/visualization/text.py

@@ -18,6 +18,7 @@
 from shutil import get_terminal_size
 import sys
 
+from qiskit.circuit import Clbit
 from qiskit.circuit import ControlledGate
 from qiskit.circuit import Reset
 from qiskit.circuit import Measure
@@ -1377,12 +1378,26 @@ def set_cl_multibox(self, creg, val, top_connect="┴"):
             top_connect (char): The char to connect the box on the top.
         """
         if self.cregbundle:
-            label = "= %s" % val
-            self.set_clbit(creg[0], BoxOnClWire(label=label, top_connect=top_connect))
+            if isinstance(creg, Clbit):
+                bit_reg = self._clbit_locations[creg]["register"]
+                bit_index = self._clbit_locations[creg]["index"]
+                label_bool = "= T" if val is True else "= F"
+                label = "%s_%s %s" % (bit_reg.name, bit_index, label_bool)
+                self.set_clbit(creg, BoxOnClWire(label=label, top_connect=top_connect))
+            else:
+                label = "= %s" % val
+                self.set_clbit(creg[0], BoxOnClWire(label=label, top_connect=top_connect))
         else:
-            clbit = [bit for bit in self.clbits if self._clbit_locations[bit]["register"] == creg]
-            cond_bin = bin(val)[2:].zfill(len(clbit))
-            self.set_cond_bullets(cond_bin, clbits=clbit)
+            if isinstance(creg, Clbit):
+                clbit = [creg]
+                cond_bin = "1" if val is True else "0"
+                self.set_cond_bullets(cond_bin, clbit)
+            else:
+                clbit = [
+                    bit for bit in self.clbits if self._clbit_locations[bit]["register"] == creg
+                ]
+                cond_bin = bin(val)[2:].zfill(len(clbit))
+                self.set_cond_bullets(cond_bin, clbits=clbit)
 
     def set_cond_bullets(self, val, clbits):
         """Sets bullets for classical conditioning when cregbundle=False.

qiskit/visualization/utils.py

@@ -21,6 +21,7 @@
 from qiskit.quantum_info.operators.symplectic import PauliTable, SparsePauliOp
 from qiskit.visualization.exceptions import VisualizationError
 from qiskit.circuit import Measure, ControlledGate, Gate, Instruction, Delay, BooleanExpression
+from qiskit.circuit import Clbit
 from qiskit.circuit.tools import pi_check
 from qiskit.exceptions import MissingOptionalLibraryError
 
@@ -298,6 +299,7 @@ def __init__(self, dag, justification, measure_map, reverse_bits):
         self.qubits = dag.qubits
         self.justification = justification
         self.measure_map = measure_map
+        self.cregs = [self.dag.cregs[reg] for reg in self.dag.cregs]
         self.reverse_bits = reverse_bits
 
         if self.justification == "left":
@@ -347,7 +349,11 @@ def slide_from_left(self, node, index):
             last_insertable_index = -1
             index_stop = -1
             if node.op.condition:
-                index_stop = self.measure_map[node.op.condition[0]]
+                if isinstance(node.op.condition[0], Clbit):
+                    cond_reg = [creg for creg in self.cregs if node.op.condition[0] in creg]
+                    index_stop = self.measure_map[cond_reg[0]]
+                else:
+                    index_stop = self.measure_map[node.op.condition[0]]
             elif node.cargs:
                 for carg in node.cargs:
                     try:

releasenotes/notes/fix-text-drawer-bit-cond-a3b02f0b0b6e3ec2.yaml

@@ -0,0 +1,8 @@
+---
+features:
+  - |
+    The ``text`` output method for the :func:`qiskit.visualization.circuit_drawer`
+    function and the :meth:`~qiskit.circuit.QuantumCircuit.draw` method can now 
+    draw circuits that contain gates with single bit condition. This was added for
+    compatibility of text drawer with the new feature of supporting classical 
+    conditioning of gates on single classical bits.

test/python/visualization/test_circuit_text_drawer.py

@@ -2909,6 +2909,58 @@ def test_text_conditional_measure(self):
 
         self.assertEqual(str(_text_circuit_drawer(circuit)), expected)
 
+    def test_text_bit_conditional(self):
+        """Test bit conditions on gates"""
+
+        qr = QuantumRegister(2, "qr")
+        cr = ClassicalRegister(2, "cr")
+        circuit = QuantumCircuit(qr, cr)
+        circuit.h(qr[0]).c_if(cr[0], 1)
+        circuit.h(qr[1]).c_if(cr[1], 0)
+
+        expected = "\n".join(
+            [
+                "         ┌───┐     ",
+                "qr_0: |0>┤ H ├─────",
+                "         └─╥─┘┌───┐",
+                "qr_1: |0>──╫──┤ H ├",
+                "           ║  └─╥─┘",
+                " cr_0: 0 ══■════╬══",
+                "           =1   ║  ",
+                " cr_1: 0 ═══════o══",
+                "                =0 ",
+            ]
+        )
+
+        self.assertEqual(str(_text_circuit_drawer(circuit)), expected)
+
+    def test_text_bit_conditional_cregbundle(self):
+        """Test bit conditions on gates when cregbundle=True"""
+
+        qr = QuantumRegister(2, "qr")
+        cr = ClassicalRegister(2, "cr")
+        circuit = QuantumCircuit(qr, cr)
+        circuit.h(qr[0]).c_if(cr[0], 1)
+        circuit.h(qr[1]).c_if(cr[1], 0)
+
+        expected = "\n".join(
+            [
+                "            ┌───┐                ",
+                "qr_0: |0>───┤ H ├────────────────",
+                "            └─╥─┘       ┌───┐    ",
+                "qr_1: |0>─────╫─────────┤ H ├────",
+                "              ║         └─╥─┘    ",
+                "         ┌────╨─────┐┌────╨─────┐",
+                " cr: 0 2/╡ cr_0 = T ╞╡ cr_1 = F ╞",
+                "         └──────────┘└──────────┘",
+            ]
+        )
+
+        self.assertEqual(
+            str(_text_circuit_drawer(circuit, cregbundle=True, vertical_compression="medium")),
+            expected,
+        )
+
     def test_text_conditional_reverse_bits_1(self):
         """Classical condition on 2q2c circuit with cregbundle=False and reverse bits"""
         qr = QuantumRegister(2, "qr")