standard gates in qiskit in its own inc file

qiskit/converters/ast_to_dag.py

@@ -200,7 +200,22 @@ def _process_custom_unitary(self, node):
         bits = [self._process_bit_id(node_element) for node_element in node.bitlist.children]
 
         if name in self.gates:
-            self._arguments(name, bits, args)
+            gargs = self.gates[name]["args"]
+            gbits = self.gates[name]["bits"]
+
+            maxidx = max(map(len, bits))
+            for idx in range(maxidx):
+                self.arg_stack.append({gargs[j]: args[j] for j in range(len(gargs))})
+                # Only index into register arguments.
+                element = [idx * x for x in [len(bits[j]) > 1 for j in range(len(bits))]]
+                self.bit_stack.append({gbits[j]: bits[j][element[j]] for j in range(len(gbits))})
+                self._create_dag_op(
+                    name,
+                    [self.arg_stack[-1][s].sym() for s in gargs],
+                    [self.bit_stack[-1][s] for s in gbits],
+                )
+                self.arg_stack.pop()
+                self.bit_stack.pop()
         else:
             raise QiskitError(
                 "internal error undefined gate:", "line=%s" % node.line, "file=%s" % node.file
@@ -209,27 +224,12 @@ def _process_custom_unitary(self, node):
     def _process_u(self, node):
         """Process a U gate node."""
         args = self._process_node(node.arguments)
-        bits = [self._process_bit_id(node.bitlist)]
-
-        self._arguments("u", bits, args)
-
-    def _arguments(self, name, bits, args):
-        gargs = self.gates[name]["args"]
-        gbits = self.gates[name]["bits"]
+        ids = self._process_bit_id(node.children[1])
 
-        maxidx = max(map(len, bits))
-        for idx in range(maxidx):
-            self.arg_stack.append({gargs[j]: args[j] for j in range(len(gargs))})
-            # Only index into register arguments.
-            element = [idx * x for x in [len(bits[j]) > 1 for j in range(len(bits))]]
-            self.bit_stack.append({gbits[j]: bits[j][element[j]] for j in range(len(gbits))})
-            self._create_dag_op(
-                name,
-                [self.arg_stack[-1][s].sym() for s in gargs],
-                [self.bit_stack[-1][s] for s in gbits],
-            )
-            self.arg_stack.pop()
-            self.bit_stack.pop()
+        for id_ in ids:
+            u_gate = UGate(*[float(arg.value) for arg in args])
+            u_gate.condition = self.condition
+            self.dag.apply_operation_back(u_gate, [id_], [])
 
     def _process_gate(self, node, opaque=False):
         """Process a gate node.

qiskit/qasm/libs/qelib1.inc

@@ -13,15 +13,9 @@ gate u1(lambda) q { U(0,0,lambda) q; }
 gate cx c,t { CX c,t; }
 // idle gate (identity)
 gate id a { U(0,0,0) a; }
-// idle gate (identity) with length gamma*sqglen
-gate u0(gamma) q { U(0,0,0) q; }
 
 // --- QE Standard Gates ---
 
-// generic single qubit gate
-gate u(theta,phi,lambda) q { U(theta,phi,lambda) q; }
-// phase gate
-gate p(lambda) q { U(0,0,lambda) q; }
 // Pauli gate: bit-flip
 gate x a { u3(pi,0,pi) a; }
 // Pauli gate: bit and phase flip
@@ -49,16 +43,10 @@ gate rz(phi) a { u1(phi) a; }
 
 // --- QE Standard User-Defined Gates  ---
 
-// sqrt(X)
-gate sx a { sdg a; h a; sdg a; }
-// inverse sqrt(X)
-gate sxdg a { s a; h a; s a; }
 // controlled-Phase
 gate cz a,b { h b; cx a,b; h b; }
 // controlled-Y
 gate cy a,b { sdg b; cx a,b; s b; }
-// swap
-gate swap a,b { cx a,b; cx b,a; cx a,b; }
 // controlled-H
 gate ch a,b {
 h b; sdg b;
@@ -78,30 +66,6 @@ gate ccx a,b,c
   cx a,b; t a; tdg b;
   cx a,b;
 }
-// cswap (Fredkin)
-gate cswap a,b,c
-{
-  cx c,b;
-  ccx a,b,c;
-  cx c,b;
-}
-// controlled rx rotation
-gate crx(lambda) a,b
-{
-  u1(pi/2) b;
-  cx a,b;
-  u3(-lambda/2,0,0) b;
-  cx a,b;
-  u3(lambda/2,-pi/2,0) b;
-}
-// controlled ry rotation
-gate cry(lambda) a,b
-{
-  ry(lambda/2) b;
-  cx a,b;
-  ry(-lambda/2) b;
-  cx a,b;
-}
 // controlled rz rotation
 gate crz(lambda) a,b
 {
@@ -119,148 +83,13 @@ gate cu1(lambda) a,b
   cx a,b;
   u1(lambda/2) b;
 }
-gate cp(lambda) a,b
-{
-  p(lambda/2) a;
-  cx a,b;
-  p(-lambda/2) b;
-  cx a,b;
-  p(lambda/2) b;
-}
 // controlled-U
 gate cu3(theta,phi,lambda) c, t
 {
   // implements controlled-U(theta,phi,lambda) with  target t and control c
-  u1((lambda+phi)/2) c;
   u1((lambda-phi)/2) t;
   cx c,t;
   u3(-theta/2,0,-(phi+lambda)/2) t;
   cx c,t;
   u3(theta/2,phi,0) t;
 }
-// controlled-sqrt(X)
-gate csx a,b { h b; cu1(pi/2) a,b; h b; }
-// controlled-U gate
-gate cu(theta,phi,lambda,gamma) c, t
-{ p(gamma) c;
-  p((lambda+phi)/2) c;
-  p((lambda-phi)/2) t;
-  cx c,t;
-  u(-theta/2,0,-(phi+lambda)/2) t;
-  cx c,t;
-  u(theta/2,phi,0) t;
-}
-// two-qubit XX rotation
-gate rxx(theta) a,b
-{
-  u3(pi/2, theta, 0) a;
-  h b;
-  cx a,b;
-  u1(-theta) b;
-  cx a,b;
-  h b;
-  u2(-pi, pi-theta) a;
-}
-// two-qubit ZZ rotation
-gate rzz(theta) a,b
-{
-  cx a,b;
-  u1(theta) b;
-  cx a,b;
-}
-// relative-phase CCX
-gate rccx a,b,c
-{
-  u2(0,pi) c;
-  u1(pi/4) c;
-  cx b, c;
-  u1(-pi/4) c;
-  cx a, c;
-  u1(pi/4) c;
-  cx b, c;
-  u1(-pi/4) c;
-  u2(0,pi) c;
-}
-// relative-phase 3-controlled X gate
-gate rc3x a,b,c,d
-{
-  u2(0,pi) d;
-  u1(pi/4) d;
-  cx c,d;
-  u1(-pi/4) d;
-  u2(0,pi) d;
-  cx a,d;
-  u1(pi/4) d;
-  cx b,d;
-  u1(-pi/4) d;
-  cx a,d;
-  u1(pi/4) d;
-  cx b,d;
-  u1(-pi/4) d;
-  u2(0,pi) d;
-  u1(pi/4) d;
-  cx c,d;
-  u1(-pi/4) d;
-  u2(0,pi) d;
-}
-// 3-controlled X gate
-gate c3x a,b,c,d
-{
-    h d;
-    p(pi/8) a;
-    p(pi/8) b;
-    p(pi/8) c;
-    p(pi/8) d;
-    cx a, b;
-    p(-pi/8) b;
-    cx a, b;
-    cx b, c;
-    p(-pi/8) c;
-    cx a, c;
-    p(pi/8) c;
-    cx b, c;
-    p(-pi/8) c;
-    cx a, c;
-    cx c, d;
-    p(-pi/8) d;
-    cx b, d;
-    p(pi/8) d;
-    cx c, d;
-    p(-pi/8) d;
-    cx a, d;
-    p(pi/8) d;
-    cx c, d;
-    p(-pi/8) d;
-    cx b, d;
-    p(pi/8) d;
-    cx c, d;
-    p(-pi/8) d;
-    cx a, d;
-    h d;
-}
-// 3-controlled sqrt(X) gate, this equals the C3X gate where the CU1 rotations are -pi/8 not -pi/4
-gate c3sqrtx a,b,c,d
-{
-    h d; cu1(-pi/8) a,d; h d;
-    cx a,b;
-    h d; cu1(pi/8) b,d; h d;
-    cx a,b;
-    h d; cu1(-pi/8) b,d; h d;
-    cx b,c;
-    h d; cu1(pi/8) c,d; h d;
-    cx a,c;
-    h d; cu1(-pi/8) c,d; h d;
-    cx b,c;
-    h d; cu1(pi/8) c,d; h d;
-    cx a,c;
-    h d; cu1(-pi/8) c,d; h d;
-}
-// 4-controlled X gate
-gate c4x a,b,c,d,e
-{
-    h e; cu1(-pi/2) d,e; h e;
-    c3x a,b,c,d;
-    h e; cu1(pi/2) d,e; h e;
-    c3x a,b,c,d;
-    c3sqrtx a,b,c,e;
-}