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Fix delay padding to respect target's constraints #10007

Merged
merged 12 commits into from
Apr 25, 2023
Merged

Fix delay padding to respect target's constraints #10007

merged 12 commits into from
Apr 25, 2023

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itoko
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@itoko itoko commented Apr 21, 2023

Summary

Fixes delay padding in transpile() function and tranpiler passes to respect target's constraints.

Details and comments

PadDelay and PadDynamicalDecoupling are fixed so that they do not pad any idle time of qubits for which the target does not support Delay instruction. For that, the parent BasePadding as well as PadDelay is updated so that it optionally takes target argument. Legacy scheduling passes ASAPSchedule and ALAPSchedule, which pad delays internally, are also fixed in the same way. In addition, transpile() is fixed to call PadDelay with a target object so that it works correctly when called with scheduling_method option.

Fixes #9993

@itoko itoko requested a review from a team as a code owner April 21, 2023 04:16
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I think this is an urgent PR, so please feel free to add commits directly if necessary. @nkanazawa1989 @mtreinish

@@ -138,7 +138,8 @@ def run(self, dag):
for bit in node.qargs:
delta = t0 - idle_before[bit]
if delta > 0:
new_dag.apply_operation_front(Delay(delta, time_unit), [bit], [])
if self.target is None or (bit_indices[bit],) in self.target.get("delay", []):
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Do we have a better way to check if an instruction is supported in a target? @mtreinish

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Umm, it may not work for a target that does not support only the delay instruction.

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There is the instruction_supported method you can use to do this lookup: https://qiskit.org/documentation/stubs/qiskit.transpiler.Target.instruction_supported.html#qiskit.transpiler.Target.instruction_supported it should handle all the edge cases around doing the lookup correctly

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coveralls commented Apr 21, 2023

Pull Request Test Coverage Report for Build 4772053053

  • 75 of 75 (100.0%) changed or added relevant lines in 8 files are covered.
  • 18 unchanged lines in 3 files lost coverage.
  • Overall coverage increased (+0.08%) to 85.999%

Files with Coverage Reduction New Missed Lines %
qiskit/transpiler/passes/synthesis/unitary_synthesis.py 1 95.37%
crates/qasm2/src/lex.rs 5 90.89%
crates/qasm2/src/parse.rs 12 97.11%
Totals Coverage Status
Change from base Build 4759571327: 0.08%
Covered Lines: 71117
Relevant Lines: 82695

💛 - Coveralls

@mtreinish mtreinish added stable backport potential The bug might be minimal and/or import enough to be port to stable Changelog: Bugfix Include in the "Fixed" section of the changelog labels Apr 21, 2023
@mtreinish mtreinish added this to the 0.24.0 milestone Apr 21, 2023
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Overall this looks great, thanks for fixing this! The approach you're doing here looks to be the best way to handle this. I left 2 comments inline, neither is really a blocker, just questions more than anything.

As a procedural point, this technically is adding a new argument to the PadDelay, PadDynamicalDecoupling and BasePadding classes which normally would not be eligible for backporting for a stable release. But for 0.24.0 #9993 was identified as an issue where the transpiler is producing incorrect output circuits with real hardware when using the scheduling_method and we need to pass the Target to the padding passes to fix this. So since we're still in the rc period I think it's ok to backport this for the 0.24.0 release as an exception to fix the high priority bug.

Comment on lines 126 to 128
if self.target is None or self.target.instruction_supported(
"delay", qargs=(bit_indices[bit],)
):
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When I started to look it this after opening #9993 I was thinking here we'd need to also handle the gates in DD sequences here besides just delays. But I think as a first step and fixing what we support in transpile() this enough. Maybe for the DD padding pass we do the additional validation of the extra sequence instructions inside the pass (as a second follow-ups PR)?

t_end=circuit_duration,
next_node=node,
prev_node=prev_node,
)
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Do you think we should log a message to indicate to users why we're not putting a delay on the the qubit (maybe DEBUG level)? I'm not sure it's needed but I'm wondering if it'll be confusing for users of the scheduling passes if they ask for scheduling and there are qubits without delays?

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LGTM, thanks for the quick updates. It'll be really good to have this fixed for 0.24.0

@mtreinish mtreinish added this pull request to the merge queue Apr 25, 2023
Merged via the queue into Qiskit:main with commit 117d188 Apr 25, 2023
mergify bot pushed a commit that referenced this pull request Apr 25, 2023
* Add and update tests

* Fix padding passes to respect target's constraints

* Fix transpile with scheduling to respect target's constraints

* Add release note

* fix reno

* use target.instruction_supported

* simplify

* Add check if all DD gates are supported on each qubit

* Add logging

* Update DD tests

* Make DD gates check target-aware

* Fix legacy DD pass

(cherry picked from commit 117d188)
jakelishman pushed a commit that referenced this pull request Apr 26, 2023
* Add and update tests

* Fix padding passes to respect target's constraints

* Fix transpile with scheduling to respect target's constraints

* Add release note

* fix reno

* use target.instruction_supported

* simplify

* Add check if all DD gates are supported on each qubit

* Add logging

* Update DD tests

* Make DD gates check target-aware

* Fix legacy DD pass

(cherry picked from commit 117d188)

Co-authored-by: Toshinari Itoko <[email protected]>
king-p3nguin pushed a commit to king-p3nguin/qiskit-terra that referenced this pull request May 22, 2023
* Add and update tests

* Fix padding passes to respect target's constraints

* Fix transpile with scheduling to respect target's constraints

* Add release note

* fix reno

* use target.instruction_supported

* simplify

* Add check if all DD gates are supported on each qubit

* Add logging

* Update DD tests

* Make DD gates check target-aware

* Fix legacy DD pass
@mtreinish mtreinish mentioned this pull request Jul 27, 2023
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Schedule padding passes don't respect target's instruction constraints
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