GraphState circuit depth excedingly high using optimization_levels 2 & 3 #5694
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I added a callback to your script and printed the depth after each pass. Basically: The issue here is the The raw output I got was: |
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In the preset passmanagers level2 and level3 the initial layout is generated by the CSP layout pass and then if an answer can't be found the specified layout method is used instead. However, as was reported in issue Qiskit#5694 the CSP layout completely misses when the trivial layout case perfectly maps the input circuit to the device. This results in level 1 significantly out performing level2 and level3 because it has to go to routing and inserts a lot of swaps. To address this hole in the CSP layout case this commit updates the preset passmanagers for level 2 and level 3 to always try a trivial layout first, if this doesn't result in a perfect mapping the pass is unchanged it will use CSP layout and then the configured layout method. Fixes Qiskit#5694
mtreinish
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In the preset passmanagers level2 and level3 the initial layout is generated by the CSP layout pass and then if an answer can't be found the specified layout method is used instead. However, as was reported in issue Qiskit#5694 the CSP layout completely misses when the trivial layout case perfectly maps the input circuit to the device. This results in level 1 significantly out performing level2 and level3 because it has to go to routing and inserts a lot of swaps. To address this hole in the CSP layout case this commit updates the preset passmanagers for level 2 and level 3 to always try a trivial layout first, if this doesn't result in a perfect mapping the pass is unchanged it will use CSP layout and then the configured layout method. Fixes Qiskit#5694
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I think this issue can be unfolded, since it uncovers several independent-but-related problems:
Possible solutions (not mutually exclusive):
While the "best of" passmanager controller would solve this for level 3 (and maybe level 2?), in my opinion all the layout selectors should be able to find the trivial layout when that's the only possible solution. If agreed, I could submit issues for each of them. |
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Actually, the problem of hiding the noise awareness (described in the last two bullets) is a problem that we currently have. PR #5075 will make CSP noise-aware. Probably |
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* Always try initial layout as first guess in preset passmanagers In the preset passmanagers level2 and level3 the initial layout is generated by the CSP layout pass and then if an answer can't be found the specified layout method is used instead. However, as was reported in issue #5694 the CSP layout completely misses when the trivial layout case perfectly maps the input circuit to the device. This results in level 1 significantly out performing level2 and level3 because it has to go to routing and inserts a lot of swaps. To address this hole in the CSP layout case this commit updates the preset passmanagers for level 2 and level 3 to always try a trivial layout first, if this doesn't result in a perfect mapping the pass is unchanged it will use CSP layout and then the configured layout method. Fixes #5694 * Tweak flow to not use trivial unless perfect * Fix lint * Add comments and explain flow Co-authored-by: Luciano Bello <[email protected]>
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Information
What is the current behavior?
The following graph state fits exactly on the device (72 CX), but
optimization_level2 or 3 transpiles it to ~950 CX gates:Steps to reproduce the problem
What is the expected behavior?
Suggested solutions
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