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Testing, deprecations, typos
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enavarro51 committed Jul 11, 2022
1 parent 2e2e8bc commit a68cef7
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Showing 4 changed files with 51 additions and 12 deletions.
6 changes: 3 additions & 3 deletions qiskit/circuit/quantumcircuit.py
Original file line number Diff line number Diff line change
Expand Up @@ -1874,11 +1874,11 @@ def draw(
specified, a new matplotlib Figure will be created and used.
Additionally, if specified there will be no returned Figure since
it is redundant.
initial_state (bool): optional. Adds ``|0>`` in the beginning of the wire.
initial_state (bool): Optional. Adds ``|0>`` in the beginning of the wire.
Default is False.
cregbundle (bool): optional. If set True, bundle classical registers.
cregbundle (bool): Optional. If set True, bundle classical registers.
Default is True.
wire_order (list): optional. A list of integers used to reorder the display
wire_order (list): Optional. A list of integers used to reorder the display
of the bits. The list must have an entry for every bit with the bits
in the range 0 to (num_qubits + num_clbits).
Expand Down
18 changes: 11 additions & 7 deletions qiskit/visualization/circuit_visualization.py
Original file line number Diff line number Diff line change
Expand Up @@ -139,11 +139,11 @@ def circuit_drawer(
specified, a new matplotlib Figure will be created and used.
Additionally, if specified there will be no returned Figure since
it is redundant.
initial_state (bool): optional. Adds ``|0>`` in the beginning of the wire.
initial_state (bool): Optional. Adds ``|0>`` in the beginning of the wire.
Default is False.
cregbundle (bool): optional. If set True, bundle classical registers.
cregbundle (bool): Optional. If set True, bundle classical registers.
Default is True.
wire_order (list): optional. A list of integers used to reorder the display
wire_order (list): Optional. A list of integers used to reorder the display
of the bits. The list must have an entry for every bit with the bits
in the range 0 to (num_qubits + num_clbits).
Expand Down Expand Up @@ -190,6 +190,10 @@ def circuit_drawer(
if output is None:
output = default_output

if wire_order is not None and reverse_bits:
raise VisualizationError(
"The wire_order option cannot be set when the reverse_bits option is True."
)
if wire_order is not None and len(wire_order) != circuit.num_qubits + circuit.num_clbits:
raise VisualizationError(
"The wire_order list must be the same "
Expand Down Expand Up @@ -327,7 +331,7 @@ def _text_circuit_drawer(
Default: ``True``.
encoding (str): Optional. Sets the encoding preference of the output.
Default: ``sys.stdout.encoding``.
wire_order (list): optional. A list of integers used to reorder the display
wire_order (list): Optional. A list of integers used to reorder the display
of the bits. The list must have an entry for every bit with the bits
in the range 0 to (num_qubits + num_clbits).
Expand Down Expand Up @@ -412,7 +416,7 @@ def _latex_circuit_drawer(
Default: `False`.
cregbundle (bool): Optional. If set True, bundle classical registers.
Default: ``False``.
wire_order (list): optional. A list of integers used to reorder the display
wire_order (list): Optional. A list of integers used to reorder the display
of the bits. The list must have an entry for every bit with the bits
in the range 0 to (num_qubits + num_clbits).
Expand Down Expand Up @@ -529,7 +533,7 @@ def _generate_latex_source(
Default: `False`.
cregbundle (bool): Optional. If set True, bundle classical registers.
Default: ``False``.
wire_order (list): optional. A list of integers used to reorder the display
wire_order (list): Optional. A list of integers used to reorder the display
of the bits. The list must have an entry for every bit with the bits
in the range 0 to (num_qubits + num_clbits).
Expand Down Expand Up @@ -617,7 +621,7 @@ def _matplotlib_circuit_drawer(
Default: `False`.
cregbundle (bool): Optional. If set True bundle classical registers.
Default: ``True``.
wire_order (list): optional. A list of integers used to reorder the display
wire_order (list): Optional. A list of integers used to reorder the display
of the bits. The list must have an entry for every bit with the bits
in the range 0 to (num_qubits + num_clbits).
Expand Down
22 changes: 20 additions & 2 deletions qiskit/visualization/utils.py
Original file line number Diff line number Diff line change
Expand Up @@ -191,7 +191,7 @@ def get_bit_register(circuit, bit):
return bit_loc.registers[0][0] if bit_loc.registers else None


def get_bit_reg_index(circuit, bit):
def get_bit_reg_index(circuit, bit, reverse_bits=None):
"""Get the register for a bit if there is one, and the index of the bit
from the top of the circuit, or the index of the bit within a register.
Expand All @@ -204,6 +204,15 @@ def get_bit_reg_index(circuit, bit):
int: index of the bit from the top of the circuit
int: index of the bit within the register, if there is a register
"""
if reverse_bits is not None:
warn(
"The 'reverse_bits' kwarg to the function "
"~qiskit.visualization.utils.get_bit_reg_index "
"is deprecated as of 0.22.0 and will be removed no earlier than 3 months "
"after the release date.",
DeprecationWarning,
2,
)
bit_loc = circuit.find_bit(bit)
bit_index = bit_loc.index
register, reg_index = bit_loc.registers[0] if bit_loc.registers else (None, None)
Expand Down Expand Up @@ -276,7 +285,7 @@ def get_wire_label(drawer, register, index, layout=None, cregbundle=True):
return wire_label


def get_condition_label_val(condition, circuit, cregbundle):
def get_condition_label_val(condition, circuit, cregbundle, reverse_bits=None):
"""Get the label and value list to display a condition
Args:
Expand All @@ -288,6 +297,15 @@ def get_condition_label_val(condition, circuit, cregbundle):
str: label to display for the condition
list(str): list of 1's and 0's indicating values of condition
"""
if reverse_bits is not None:
warn(
"The 'reverse_bits' kwarg to the function "
"~qiskit.visualization.utils.get_condition_label_val "
"is deprecated as of 0.22.0 and will be removed no earlier than 3 months "
"after the release date.",
DeprecationWarning,
2,
)
cond_is_bit = bool(isinstance(condition[0], Clbit))
cond_val = int(condition[1])

Expand Down
17 changes: 17 additions & 0 deletions test/python/visualization/test_circuit_drawer.py
Original file line number Diff line number Diff line change
Expand Up @@ -102,3 +102,20 @@ def test_latex_output_file_correct_format(self):
else:
self.assertIn(im.format.lower(), filename.split(".")[-1])
os.remove(filename)

def test_wire_order_raises(self):
"""Verify we raise if using wire order incorrectly."""

circuit = QuantumCircuit(3, 3)
circuit.x(1)
with self.assertRaisesRegex(VisualizationError, "the same length as"):
visualization.circuit_drawer(circuit, wire_order=[0, 1, 2])

with self.assertRaisesRegex(VisualizationError, "one and only one entry"):
visualization.circuit_drawer(circuit, wire_order=[2, 1, 0, 3, 1, 5])

with self.assertRaisesRegex(VisualizationError, "cannot be set when the reverse_bits"):
visualization.circuit_drawer(circuit, wire_order=[0, 1, 2, 5, 4, 3], reverse_bits=True)

with self.assertWarnsRegex(RuntimeWarning, "Cregbundle set"):
visualization.circuit_drawer(circuit, cregbundle=True, wire_order=[0, 1, 2, 5, 4, 3])

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