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Add dynamical decoupling pass #367

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merged 73 commits into from
Aug 24, 2022

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taalexander
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Summary

This PR adds a dynamical decoupling pass for IBM dynamical circuit backends. It is based on the contents of #365 and should only be merged after.

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coveralls commented Jul 7, 2022

Pull Request Test Coverage Report for Build 2837041673

  • 322 of 339 (94.99%) changed or added relevant lines in 7 files are covered.
  • No unchanged relevant lines lost coverage.
  • Overall coverage increased (+3.6%) to 36.844%

Changes Missing Coverage Covered Lines Changed/Added Lines %
qiskit_ibm_provider/transpiler/passes/scheduling/block_base_padder.py 93 96 96.88%
qiskit_ibm_provider/transpiler/passes/scheduling/scheduler.py 92 95 96.84%
qiskit_ibm_provider/transpiler/passes/scheduling/dynamical_decoupling.py 112 123 91.06%
Totals Coverage Status
Change from base Build 2799611551: 3.6%
Covered Lines: 2169
Relevant Lines: 5887

💛 - Coveralls

dd_sequence: Sequence of gates to apply in idle spots.
qubits: Physical qubits on which to apply DD.
If None, all qubits will undergo DD (when possible).
spacing: A list of spacings between the DD gates.
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@reza-j reza-j Jul 8, 2022

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Why do we need spacing between DD gates? I'm wondering if the DD gates still adds to identity if there are delays between them?

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this is sort of the definition of DD where you take a long delay and break it up into some different chunks. those chunks are the spacing here. They are identity for circuit transformation purposes.

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Thanks, Ali! :)

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# (3) Construct DD sequence with delays
num_elements = max(len(self._dd_sequence), len(taus))
idle_after = t_start
for dd_ind in range(num_elements):
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@reza-j reza-j Jul 8, 2022

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Here, we insert DD gates interleaved with delays (i.e., taus), right? Is there a scenario where len(self._dd_sequence)>len(taus), and we insert two DD gates with no delay in between? Do we need to check for that scenario and raise an error?

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@taalexander taalexander Aug 11, 2022

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Please see the condition below if dd_ind < len(taus) and if dd_ind < len(self._dd_sequence): which effectively perform this error handling.

Comment on lines 188 to 202
# Check if DD sequence is identity
if num_pulses != 1:
if num_pulses % 2 != 0:
raise TranspilerError(
"DD sequence must contain an even number of gates (or 1)."
)
noop = np.eye(2)
for gate in self._dd_sequence:
noop = noop.dot(gate.to_matrix())
if not matrix_equal(noop, IGate().to_matrix(), ignore_phase=True):
raise TranspilerError(
"The DD sequence does not make an identity operation."
)
self._sequence_phase = np.angle(noop[0][0])
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Here, we multiply the DD gates to see if they add to identity. How about the delays we add in between the DD gates? Don't we need to multiply them as well?

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The delay operation is the identity if we're in the frame of the qubits.

@taalexander taalexander force-pushed the add-dynamical-decoupling-pass branch from f53474a to 065b71d Compare August 11, 2022 02:49
@taalexander taalexander requested review from ajavadia and reza-j August 11, 2022 02:49
@kt474 kt474 merged commit 3a2a7f2 into Qiskit:main Aug 24, 2022
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Just a heads up related to this we're adding a backend interface for backend's to specify custom compilation stages: Qiskit/qiskit#8648 this is probably a good fit for this pass. Once that is released we should update dynamic circuits backends to add the hook point so that by default transpile() will always run this DD pass for the scheduling stage when targeting the backend.

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8 participants