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Merge remote-tracking branch 'origin/devel' into flexible-types
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jvesely committed Nov 8, 2021
2 parents 22fa345 + 3813c13 commit 39bb028
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Showing 17 changed files with 996 additions and 414 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -181,7 +181,7 @@ def print_weights():
print('ControlSignal variables: ', [sig.parameters.variable.get(i) for sig in lvoc.control_signals])
print('ControlSignal values: ', [sig.parameters.value.get(i) for sig in lvoc.control_signals])
# print('state_features: ', lvoc.get_feature_values(context=c))
print('lvoc: ', lvoc.evaluation_function([sig.parameters.variable.get(i) for sig in lvoc.control_signals], context=i))
print('lvoc: ', lvoc.evaluate_agent_rep([sig.parameters.variable.get(i) for sig in lvoc.control_signals], context=i))
# print('time: ', duration)
print('--------------------')

Expand Down Expand Up @@ -222,6 +222,6 @@ def print_weights():
# print('ControlSignal variables: ', [sig.parameters.variable.get(c) for sig in lvoc.control_signals])
# print('ControlSignal values: ', [sig.parameters.value.get(c) for sig in lvoc.control_signals])
# # print('state_features: ', lvoc.get_feature_values(context=c))
# print('lvoc: ', lvoc.evaluation_function([sig.parameters.variable.get(c) for sig in lvoc.control_signals], context=c))
# print('lvoc: ', lvoc.evaluate_agent_rep([sig.parameters.variable.get(c) for sig in lvoc.control_signals], context=c))
# print('time: ', duration)
# print('--------------------')
Original file line number Diff line number Diff line change
Expand Up @@ -232,7 +232,7 @@ def print_weights():
print('ControlSignal variables: ', [sig.parameters.variable.get(i) for sig in lvoc.control_signals])
print('ControlSignal values: ', [sig.parameters.value.get(i) for sig in lvoc.control_signals])
# print('state_features: ', lvoc.state_feature_values)
# print('lvoc: ', lvoc.evaluation_function([sig.parameters.variable.get(i) for sig in lvoc.control_signals], context=i))
# print('lvoc: ', lvoc.evaluate_agent_rep([sig.parameters.variable.get(i) for sig in lvoc.control_signals], context=i))
# print('time: ', duration)
print('--------------------')

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8 changes: 0 additions & 8 deletions psyneulink/core/components/component.py
Original file line number Diff line number Diff line change
Expand Up @@ -1697,16 +1697,8 @@ def _deferred_init(self, **kwargs):
self._init_args.update(kwargs)

# Complete initialization
# MODIFIED 10/27/18 OLD:
super(self.__class__,self).__init__(**self._init_args)

# MODIFIED 10/27/18 NEW: FOLLOWING IS NEEDED TO HANDLE FUNCTION DEFERRED INIT (JDC)
# try:
# super(self.__class__,self).__init__(**self._init_args)
# except:
# self.__init__(**self._init_args)
# MODIFIED 10/27/18 END

# If name was assigned, "[DEFERRED INITIALIZATION]" was appended to it, so remove it
if DEFERRED_INITIALIZATION in self.name:
self.name = self.name.replace("[" + DEFERRED_INITIALIZATION + "]", "")
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6 changes: 3 additions & 3 deletions psyneulink/core/components/mechanisms/mechanism.py
Original file line number Diff line number Diff line change
Expand Up @@ -1380,20 +1380,20 @@ class Mechanism_Base(Mechanism):
projections : ContentAddressableList
a list of all of the Mechanism's `Projections <Projection>`, composed from the
`path_afferents <InputPorts.path_afferents>` of all of its `input_ports <Mechanism_Base.input_ports>`,
`path_afferents <Port.path_afferents>` of all of its `input_ports <Mechanism_Base.input_ports>`,
the `mod_afferents` of all of its `input_ports <Mechanism_Base.input_ports>`,
`parameter_ports <Mechanism)Base.parameter_ports>`, and `output_ports <Mechanism_Base.output_ports>`,
and the `efferents <Port.efferents>` of all of its `output_ports <Mechanism_Base.output_ports>`.
afferents : ContentAddressableList
a list of all of the Mechanism's afferent `Projections <Projection>`, composed from the
`path_afferents <InputPorts.path_afferents>` of all of its `input_ports <Mechanism_Base.input_ports>`,
`path_afferents <Port.path_afferents>` of all of its `input_ports <Mechanism_Base.input_ports>`,
and the `mod_afferents` of all of its `input_ports <Mechanism_Base.input_ports>`,
`parameter_ports <Mechanism)Base.parameter_ports>`, and `output_ports <Mechanism_Base.output_ports>`.,
path_afferents : ContentAddressableList
a list of all of the Mechanism's afferent `PathwayProjections <PathwayProjection>`, composed from the
`path_afferents <InputPorts.path_afferents>` attributes of all of its `input_ports
`path_afferents <Port.path_afferents>` attributes of all of its `input_ports
<Mechanism_Base.input_ports>`.
mod_afferents : ContentAddressableList
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Original file line number Diff line number Diff line change
Expand Up @@ -833,6 +833,8 @@ def monitored_output_ports_weights_and_exponents(self):
def monitored_output_ports_weights_and_exponents(self, weights_and_exponents_tuples):
self.monitor_weights_and_exponents = weights_and_exponents_tuples

# FIX: 11/3/21 -- MOVE THIS TO ControlMechanism, AND INTEGRATE WITH ControlMechanism.validate_monitored_port_spec()
# OR MOVE THAT METHOD TO HERE??
def _parse_monitor_specs(monitor_specs):
spec_tuple = namedtuple('SpecTuple', 'index spec')
parsed_specs = []
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13 changes: 10 additions & 3 deletions psyneulink/core/components/ports/port.py
Original file line number Diff line number Diff line change
Expand Up @@ -1766,7 +1766,12 @@ def _get_receiver_port(spec):
context=context)
# Match the projection's value with the value of the function parameter
# should be defaults.value?
mod_proj_spec_value = type_match(projection.value, type(mod_param_value))
try:
mod_proj_spec_value = type_match(projection.value, type(mod_param_value))
except TypeError as error:
raise PortError(f"The value for {self.name} of {self.owner.name} ({projection.value}) does "
f"not match the format ({mod_param_value}) of the Parameter it modulates "
f"({receiver.owner.name}[{mod_param_name}]).")
if (mod_param_value is not None
and not iscompatible(mod_param_value, mod_proj_spec_value)):
raise PortError(f"Output of {projection.name} ({mod_proj_spec_value}) is not compatible "
Expand Down Expand Up @@ -3260,8 +3265,10 @@ def _parse_port_spec(port_type=None,
# port_dict[OWNER].name, spec_function_value, spec_function))

if port_dict[REFERENCE_VALUE] is not None and not iscompatible(port_dict[VALUE], port_dict[REFERENCE_VALUE]):
raise PortError("Port value ({}) does not match reference_value ({}) for {} of {})".
format(port_dict[VALUE], port_dict[REFERENCE_VALUE], port_type.__name__, owner.name))
port_name = f"the {port_dict[NAME]}" if (NAME in port_dict and port_dict[NAME]) else f"an"
raise PortError(f"The value ({port_dict[VALUE]}) for {port_name} {port_type.__name__} of "
f"{owner.name} does not match the reference_value ({port_dict[REFERENCE_VALUE]}) "
f"used for it at construction.")

return port_dict

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