This project contains a RISC-V 5-stage in-order core with an Sv39 MMU, supporting Integer and Multiplication extensions. To debug the core, I also developed an RV64 emulator in C for differential testing against the core (https://github.com/PorterLu/sustemu).
generated from chipsalliance/chisel-template
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PorterLu/NiCore
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