Requires 2.x rootfs, server, webcontrol
- Update to Python3
- Increase SRGATES from 2 to 4
- Remove POSENC and QDEC from default Blocks
- Add HEALTH for encoders
- Less entries on PosBus trims FPGA image size
- Added SFP3 SYNC
- Split FMC inputs and outputs into 2 Blocks
- Fix PCAP logic when interrupted in a gate and restarted
- Added NPULSES to PULSE Block for pulse train output
- Reduce size of PULSE queue to 256
- Fix Monitor cards to not need anything set on OUTENC Blocks
- Remove PCAP_DATA_DELAY
