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19 Open 13 Closed
19 Open 13 Closed
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Issues list

pll primitives
#34 opened Feb 17, 2021 by Nic30
Tests for MultiConfigUnitWrapper with hierarchical interfaces
#31 opened Jan 25, 2021 by Nic30
Merge Axi_r/wDatapump, StructReader/Write, ArrayItemGetter and other bus frame logic
#30 opened Jan 11, 2021 by Nic30
Tests for top of AxiInterconnectMatrix
#29 opened Dec 4, 2020 by Nic30 v3.0
DSP mapper examples
#28 opened Nov 26, 2020 by Nic30 v3.0
Intel DSP primitives
#26 opened Nov 26, 2020 by Nic30 v3.0
AXI cache + LSU verification of whole complex
#25 opened Nov 26, 2020 by Nic30 v3.0
Examples do not work out of the box (automatic test against pip required for check if new release of dependency is required)
#23 opened Jul 30, 2020 by philipaxer v3.0
4
RLE-encoding for DebugBusMonitor
#22 opened Apr 10, 2020 by Nic30
AXI interconnect: variant with customizable topology
#21 opened Jan 7, 2020 by Nic30
ETH MAC SFP/RGMII example
#18 opened Jan 7, 2020 by Nic30
2
OV7670 or other common cammera example
#17 opened Jan 7, 2020 by Nic30
Normalization of m/s, master/slave, din,dout...
#15 opened Jan 7, 2020 by Nic30
1
usb: 1.0 phy (softcore) and USB3300 (ULPI based USB 2.0 phy IC)
#14 opened Jan 7, 2020 by Nic30
1
Counting bloom filter
#13 opened Dec 19, 2019 by Nic30
pci-e endpoint (slave) and pci-e stream DMA enhancement
#10 opened Jan 14, 2019 by Nic30
1
JTAG endpoint and interconnect
#9 opened Jul 7, 2017 by Nic30
2
endianity for endpoint
#8 opened Jun 27, 2017 by Nic30
Make SPI endpoint universal and configurable as QSPI
#4 opened Apr 28, 2017 by Nic30
@Nic30
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