Remove trailing spaces at the end of lines.

Mediumcore · Aug 13, 2018 · 8c61c2f · 8c61c2f
1 parent 81c6bda
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Showing 71 changed files with 153 additions and 153 deletions.
diff --git a/ChangeLog b/ChangeLog
@@ -18170,7 +18170,7 @@
 	  almost complete... still lacking GPIO support and LED support.  There are
 	  still no significant drivers available.
 	* SMP: Introduce spin_lock_irqsave() and spin_unlock_irqrestore().  These
-	  APIs are simplified version of enter_critical_section() and 
+	  APIs are simplified version of enter_critical_section() and
 	  leave_critical_section() to protect data (e.g. registers) in SMP mode.  By
 	  using these APIs inside drivers, performance will be improved.  From
 	  Masayuki Ishikawa (2017-12-07).
@@ -18660,7 +18660,7 @@
 	  longer returns an errno.  From Gregory Nutt (2018-01-31).
 	* graphics/:  Review return values for all calls to kthread_start() because
 	  it no longer returns an errno.  From Gregory Nutt (2018-01-31).
-	* sched/:  Convert legitimate uses of task_create() to nxtask_create(). 
+	* sched/:  Convert legitimate uses of task_create() to nxtask_create().
 	  Review handling of returned values from all uses of kthread_create() (as
 	  well as nxtask_create()).  From Gregory Nutt (2018-01-31).
 	* arm/src/kinetis:  Correct some Ethernet PHY register bit tests for the
@@ -18815,7 +18815,7 @@
 	  Mayencourt (2018-02-19).
 	* drivers/mtd:  mtd_config.c:  Add still more error handling (to detect bad
 	  underlying flash implementations).  Remove MTD_ERASE that was erasing data
-	  block instead of erase block.  This is a partial revert of 4f18b4. 
+	  block instead of erase block.  This is a partial revert of 4f18b4.
 	  Reported-by: Pascal Speck <[email protected]>
 	* arch/arm/src/stm32l4:  stm32l4_flash: change flash programming to use
 	  page buffer for unaligned writes.  From Juha Niskanen (2018-02-19).

diff --git a/Documentation/NuttxPortingGuide.html b/Documentation/NuttxPortingGuide.html
@@ -487,7 +487,7 @@ <h1>2.0 <a name="DirectoryStructure">Directory Structure</a></h1>
       As an example, all ARM processor architectures are provided under the <code>arch/arm/</code> directory which is selected with the <code>CONFIG_ARCH=&quot;arm&quot;</code> configuration option.
     </p>
     <p>
-      Variants of the processor architecture may be provided in sub-directories of the 
+      Variants of the processor architecture may be provided in sub-directories of the
       Extending this example, the ARMv7-M ARM family is supported by logic in <code>arch/arm/include/armv7-m</code> and <code>arch/arm/src/armv7-m</code> directories which are selected by the <code>CONFIG_ARCH_CORTEXM3=y</code>, <code>CONFIG_ARCH_CORTEXM4=y</code>, or  <code>CONFIG_ARCH_CORTEXM7=y</code> configuration options
     </p>
   </li>

diff --git a/arch/arm/include/stm32f7/stm32f72xx73xx_irq.h b/arch/arm/include/stm32f7/stm32f72xx73xx_irq.h
@@ -33,8 +33,8 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *Change Record:
- * bf20171107 Created file. It's identical to stm32f74xx75xx_irq except for the 
- *             exclusions noted by this tag, and the addition of the last IRQ 
+ * bf20171107 Created file. It's identical to stm32f74xx75xx_irq except for the
+ *             exclusions noted by this tag, and the addition of the last IRQ
  *             for SDMMC2 (IRQ103).
  ****************************************************************************************************/
 

diff --git a/arch/arm/src/armv7-a/arm_vectors.S b/arch/arm/src/armv7-a/arm_vectors.S
@@ -62,7 +62,7 @@ g_undeftmp:
 g_aborttmp:
 	.word	0		/* Saved lr */
 	.word	0		/* Saved spsr */
-    
+
 #ifdef CONFIG_ARMV7A_DECODEFIQ
 g_fiqtmp:
 	.word	0		/* Saved lr */

diff --git a/arch/arm/src/lc823450/lc823450_mtd.h b/arch/arm/src/lc823450/lc823450_mtd.h
@@ -71,7 +71,7 @@
 #define LC823450_PART5_START    (LC823450_PART4_START + LC823450_PART4_NBLOCKS)
 #define LC823450_PART5_NBLOCKS  32768
 #define LC823450_PART6_START    (LC823450_PART5_START + LC823450_PART5_NBLOCKS)
-#define LC823450_PART6_NBLOCKS  131072 
+#define LC823450_PART6_NBLOCKS  131072
 #define LC823450_PART7_START    (LC823450_PART6_START + LC823450_PART6_NBLOCKS)
 #define LC823450_PART7_NBLOCKS  32768
 #define LC823450_PART8_START    (LC823450_PART7_START + LC823450_PART7_NBLOCKS)

diff --git a/arch/arm/src/lc823450/lc823450_sddrv_if.h b/arch/arm/src/lc823450/lc823450_sddrv_if.h
@@ -251,7 +251,7 @@ SINT_T fixedSdDrReadSector(UI_32 addr, UI_32 cnt, void *buf, SINT_T type,
                            struct SdDrCfg_s *cfg);
 
 UI_32 sdif_get_status(UI_32);
-  
+
 #if defined(__cplusplus)
 }
 #endif

diff --git a/arch/arm/src/lc823450/lc823450_serial.c b/arch/arm/src/lc823450/lc823450_serial.c
@@ -280,7 +280,7 @@ static uart_dev_t g_uart0port =
     .size   = CONFIG_UART0_RXBUFSIZE,
     .buffer = g_uart0rxbuffer,
   },
-  .xmit     = 
+  .xmit     =
   {
     .size   = CONFIG_UART0_TXBUFSIZE,
     .buffer = g_uart0txbuffer,

diff --git a/arch/arm/src/lpc54xx/lpc54_emc.c b/arch/arm/src/lpc54xx/lpc54_emc.c
@@ -491,7 +491,7 @@ void lpc54_emc_sram_initialize(FAR uint32_t *extwait,
   unsigned int i;
 
   /* Initialize extended wait. */
- 
+
   DEBUGASSERT(statconfig != NULL && nchips > 0);
 
   if (extwait)

diff --git a/arch/arm/src/lpc54xx/lpc54_emc.h b/arch/arm/src/lpc54xx/lpc54_emc.h
@@ -175,7 +175,7 @@ struct emc_static_chip_config_s
                           * read access in units of nanoseconds */
   uint32_t waitreadpage; /* In page mode, the read after the first read
                           * wait states in units of nanoseconds */
-  uint32_t waitwrite;    /* The delay from chip select to write access in 
+  uint32_t waitwrite;    /* The delay from chip select to write access in
                           * units of nanoseconds */
   uint32_t waitturn;     /* The Bus turn-around time in units of
                           * nanoseconds */

diff --git a/arch/arm/src/samd2l2/sam_usb.c b/arch/arm/src/samd2l2/sam_usb.c
@@ -3793,16 +3793,16 @@ static void sam_hw_setup(struct sam_usbdev_s *priv)
 
   /* Load USB factory calibration values from NVRAM */
 
-  calib_transn = getreg32(SYSCTRL_FUSES_USBTRANSN_ADDR) & 
+  calib_transn = getreg32(SYSCTRL_FUSES_USBTRANSN_ADDR) &
                  SYSCTRL_FUSES_USBTRANSN_MASK >> SYSCTRL_FUSES_USBTRANSN_SHIFT;
 
-  calib_transp = getreg32(SYSCTRL_FUSES_USBTRANSP_ADDR) & 
+  calib_transp = getreg32(SYSCTRL_FUSES_USBTRANSP_ADDR) &
                  SYSCTRL_FUSES_USBTRANSP_MASK >> SYSCTRL_FUSES_USBTRANSP_SHIFT;
 
   calib_trim = getreg32(SYSCTRL_FUSES_USBTRIM_ADDR) &
                SYSCTRL_FUSES_USBTRIM_MASK >> SYSCTRL_FUSES_USBTRIM_SHIFT;
 
-  padcalib = USB_PADCAL_TRANSP(calib_transp) | 
+  padcalib = USB_PADCAL_TRANSP(calib_transp) |
              USB_PADCAL_TRANSN(calib_transn) |
              USB_PADCAL_TRIM(calib_trim);
 

diff --git a/arch/arm/src/samd5e5/chip/sam_usart.h b/arch/arm/src/samd5e5/chip/sam_usart.h
@@ -294,7 +294,7 @@
 #define USART_CTRLC_BRKLEN_SHIFT     (8)       /* Bits 8-9: LIN Master Break Length */
 #define USART_CTRLC_BRKLEN_MASK      (3 << USART_CTRLC_BRKLEN_SHIFT)
 #  define USART_CTRLC_BRKLEN_13BITS  (0 << USART_CTRLC_BRKLEN_SHIFT) /* 13 bit times */
-#  define USART_CTRLC_BRKLEN_17BITS  (1 << USART_CTRLC_BRKLEN_SHIFT) /* 17 bit times */ 
+#  define USART_CTRLC_BRKLEN_17BITS  (1 << USART_CTRLC_BRKLEN_SHIFT) /* 17 bit times */
 #  define USART_CTRLC_BRKLEN_21BITS  (2 << USART_CTRLC_BRKLEN_SHIFT) /* 21 bit times */
 #  define USART_CTRLC_BRKLEN_26BITS  (3 << USART_CTRLC_BRKLEN_SHIFT) /* 26 bit times */
 #define USART_CTRLC_HDRDLY_SHIFT     (10)      /* Bits 10-11: LIN Master Header Delay */

diff --git a/arch/arm/src/stm32/chip.h b/arch/arm/src/stm32/chip.h
@@ -47,7 +47,7 @@
 #include <arch/stm32/chip.h>
 
 /* Include the chip interrupt definition file */
- 
+
 #include <arch/stm32/irq.h>
 
 /* Include the chip pin configuration file */

diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_rcc.h
@@ -140,7 +140,7 @@
 #  define RCC_PLLCFG_PLLN(n)         ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 2..432 */
 #define RCC_PLLCFG_PLLP_SHIFT        (16)      /* Bits 16-17: Main PLL (PLL) main system clock divider */
 #define RCC_PLLCFG_PLLP_MASK         (3 << RCC_PLLCFG_PLLP_SHIFT)
-#  define RCC_PLLCFG_PLLP(n)         ((((n)>>1)-1)<< RCC_PLLCFG_PLLP_SHIFT) /* n=2,4,6,8 */ 
+#  define RCC_PLLCFG_PLLP(n)         ((((n)>>1)-1)<< RCC_PLLCFG_PLLP_SHIFT) /* n=2,4,6,8 */
 #  define RCC_PLLCFG_PLLP_2          (0 << RCC_PLLCFG_PLLP_SHIFT) /* 00: PLLP = 2 */
 #  define RCC_PLLCFG_PLLP_4          (1 << RCC_PLLCFG_PLLP_SHIFT) /* 01: PLLP = 4 */
 #  define RCC_PLLCFG_PLLP_6          (2 << RCC_PLLCFG_PLLP_SHIFT) /* 10: PLLP = 6 */

diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_syscfg.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_syscfg.h
@@ -54,7 +54,7 @@
 
 #define STM32_SYSCFG_MEMRMP_OFFSET    0x0000 /* SYSCFG memory remap register */
 #define STM32_SYSCFG_PMC_OFFSET       0x0004 /* SYSCFG peripheral mode configuration register */
- 
+
 #define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
 #define STM32_SYSCFG_EXTICR1_OFFSET   0x0008 /* SYSCFG external interrupt configuration register 1 */
 #define STM32_SYSCFG_EXTICR2_OFFSET   0x000c /* SYSCFG external interrupt configuration register 2 */

diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_uart.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_uart.h
@@ -44,7 +44,7 @@
 
 #include <nuttx/config.h>
 
-#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) 
+#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
 
 /************************************************************************************
  * Pre-processor Definitions

diff --git a/arch/arm/src/stm32f7/stm32_dma2d.c b/arch/arm/src/stm32f7/stm32_dma2d.c
@@ -735,7 +735,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha,
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
- 
+
 /****************************************************************************
  * Name: stm32_dma2d_setclut
  *

diff --git a/arch/avr/include/avr32/irq.h b/arch/avr/include/avr32/irq.h
@@ -185,7 +185,7 @@ static inline irqstate_t up_irq_save(void)
 /* Restore saved interrupt state */
 
 static inline void up_irq_restore(irqstate_t flags)
-{ 
+{
   if ((flags & AVR32_SR_GM_MASK) == 0)
     {
       __asm__ __volatile__ (

diff --git a/arch/or1k/include/spr.h b/arch/or1k/include/spr.h
@@ -232,7 +232,7 @@
 
 #define SPR_CPUCFGR_NSGF_SHIFT  (0)
 #define SPR_CPUCFGR_NSGF_MASK   (0xf << SPR_CPUCFGR_NSGF_SHIFT)
-#define SPR_CPUCFGR_CGF         (1 << 4) 
+#define SPR_CPUCFGR_CGF         (1 << 4)
 #define SPR_CPUCFGR_OB32S       (1 << 5)                /* ORBIS32 Supported */
 #define SPR_CPUCFGR_OB64S       (1 << 6)                /* ORBIS64 Supported */
 #define SPR_CPUCFGR_OF32S       (1 << 7)                /* ORFPX32 Supported */

diff --git a/arch/or1k/src/common/up_task_start.c b/arch/or1k/src/common/up_task_start.c
@@ -77,7 +77,7 @@
 void up_task_start(main_t taskentry, int argc, FAR char *argv[])
 {
   /* Let sys_call3() do all of the work */
-  
+
   sinfo("entry %p argc %d\n", taskentry, argc);
 
   sys_call3(SYS_task_start, (uintptr_t)taskentry, (uintptr_t)argc,

diff --git a/arch/or1k/src/common/up_timer.c b/arch/or1k/src/common/up_timer.c
@@ -77,7 +77,7 @@ static int or1k_timer_isr(int irq, uint32_t *regs, void *arg)
   mtspr(SPR_TICK_TTMR, ttmr);
 
   sched_process_timer();
-  
+
   return OK;
 }
 
@@ -89,7 +89,7 @@ static int or1k_timer_isr(int irq, uint32_t *regs, void *arg)
  * Name: or1k_timer_initialize
  *
  * Description:
- *   Initialize the OpenRISC Tick Timer unit  
+ *   Initialize the OpenRISC Tick Timer unit
  *
  ****************************************************************************/
 
@@ -104,6 +104,6 @@ void or1k_timer_initialize(void)
   mtspr(SPR_TICK_TTCR, 0);
 
   /* Write TTMR */
-  
-  mtspr(SPR_TICK_TTMR, ttmr); 
+
+  mtspr(SPR_TICK_TTMR, ttmr);
 }
diff --git a/arch/or1k/src/mor1kx/Make.defs b/arch/or1k/src/mor1kx/Make.defs
@@ -81,7 +81,7 @@ ifeq ($(CONFIG_DEBUG_FEATURES),y)
 endif
 
 CHIP_ASRCS  =
-CHIP_CSRCS  = 
+CHIP_CSRCS  =
 
 ifneq ($(CONFIG_SCHED_TICKLESS),y)
 #CHIP_CSRCS += sam_timerisr.c

diff --git a/arch/or1k/src/mor1kx/up_vectortab.S b/arch/or1k/src/mor1kx/up_vectortab.S
@@ -250,7 +250,7 @@ _reset_vector:
   /* Set the stack pointer */
 
   l.movhi r1,hi(_ebss);
-  l.ori   r1,r1,lo(_ebss); 
+  l.ori   r1,r1,lo(_ebss);
   l.addi  r1,r1,CONFIG_IDLETHREAD_STACKSIZE-4;
   l.ori   r2,r1,0;
   l.nop
@@ -262,7 +262,7 @@ _reset_vector:
   l.nop;
 
   /* Should never reach here */
-  
+
   l.j 0;
   l.nop;
 
@@ -281,15 +281,15 @@ _data_page_fault:
   l.nop;
   l.j 0;
   l.nop;
- 
+
   /* Instruction page fault */
 
   .org 0x400
 _instruction_page_fault:
   l.nop;
   l.j 0;
   l.nop;
-  
+
   /* Tick Timer */
 
   .org 0x500
@@ -354,7 +354,7 @@ _itlb_miss:
 
   /* Range exception */
 
-  .org 0xB00 
+  .org 0xB00
 _range_exception:
   l.nop;
   l.j 0;

diff --git a/configs/bambino-200e/src/lpc43_max31855.c b/configs/bambino-200e/src/lpc43_max31855.c
@@ -96,7 +96,7 @@ int lpc43_max31855initialize(FAR const char *devpath, int bus, uint16_t devid)
     {
       snerr("ERROR: Error registering MAX31855\n");
     }
-    
+
   return ret;
 }
 

diff --git a/configs/bambino-200e/src/lpc43_ssp.c b/configs/bambino-200e/src/lpc43_ssp.c
@@ -76,12 +76,12 @@ void weak_function lpc43_sspdev_initialize(void)
     {
       snerr("ERROR: Error configuring chip select GPIO pin\n");
     }
-    
+
   lpc43_pin_config(PINCONFIG_MAX31855_CS2);
   ret = lpc43_gpio_config(GPIO_MAX31855_CS2);
   if (ret < 0)
     {
-      snerr("ERROR: Error configuring chip select GPIO pin\n")  
+      snerr("ERROR: Error configuring chip select GPIO pin\n")
     }
 #endif
 }
@@ -108,7 +108,7 @@ void lpc43_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
     {
       lpc43_gpio_write(GPIO_MAX31855_CS1, !selected);
     }
-    
+
   if (devid == SPIDEV_TEMPERATURE(1))
     {
       lpc43_gpio_write(GPIO_MAX31855_CS2, !selected);
@@ -157,7 +157,7 @@ void lpc43_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
     {
       lpc43_gpio_write(GPIO_MAX31855_CS1, !selected);
     }
-    
+
   if (devid == SPIDEV_TEMPERATURE(1))
     {
       lpc43_gpio_write(GPIO_MAX31855_CS2, !selected);

diff --git a/configs/imxrt1050-evk/src/imxrt_buttons.c b/configs/imxrt1050-evk/src/imxrt_buttons.c
@@ -18,7 +18,7 @@
  *    used to endorse or promote products derived from this software
  *    without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORSMULTILINK 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

diff --git a/configs/lc823450-xgevk/README.txt b/configs/lc823450-xgevk/README.txt
@@ -57,12 +57,12 @@ index 687f50ca..8418eff8 100644
 +++ b/examples/ostest/waitpid.c
 @@ -54,7 +54,7 @@
   ****************************************************************************/
- 
+
  #define RETURN_STATUS 14
 -#define NCHILDREN     3
 +#define NCHILDREN     2
  #define PRIORITY      100
- 
+
  /****************************************************************************
 
 Other Status

diff --git a/configs/lpc4357-evb/README.txt b/configs/lpc4357-evb/README.txt
@@ -373,7 +373,7 @@ FPU Configuration Options
 -------------------------
 
 There are two version of the FPU support built into the most NuttX Cortex-M4
-ports. 
+ports.
 
 1. Non-Lazy Floating Point Register Save
 

diff --git a/configs/metro-m4/src/sam_autoleds.c b/configs/metro-m4/src/sam_autoleds.c
@@ -53,7 +53,7 @@
  *   ------------------- ---------------------------- ------
  *   SYMBOL                  Meaning                  LED
  *   ------------------- ---------------------------- ------
- *   
+ *
  *   LED_STARTED         NuttX has been started       OFF
  *   LED_HEAPALLOCATE    Heap has been allocated      OFF
  *   LED_IRQSENABLED     Interrupts enabled           OFF

diff --git a/configs/metro-m4/src/sam_boot.c b/configs/metro-m4/src/sam_boot.c
@@ -55,7 +55,7 @@
  * Name: sam_board_initialize
  *
  * Description:
- *   All SAMD5/E5 architectures must provide the following entry point. 
+ *   All SAMD5/E5 architectures must provide the following entry point.
  *   This entry point is called early in the initialization -- after all
  *   memory has been configured and mapped but before any devices have been
  *   initialized.

diff --git a/configs/nucleo-f410rb/include/board.h b/configs/nucleo-f410rb/include/board.h
@@ -146,7 +146,7 @@
 #define STM32_APB2_TIM11_CLKIN  (STM32_PCLK2_FREQUENCY)
 
 /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
- * otherwise frequency is 2xAPBx. 
+ * otherwise frequency is 2xAPBx.
  * Note: TIM1,9,11 are on APB2, others on APB1
  */
 /* REVISIT */

diff --git a/configs/nucleo-f410rb/src/stm32_boot.c b/configs/nucleo-f410rb/src/stm32_boot.c
@@ -80,7 +80,7 @@ void stm32_boardinitialize(void)
 
 #ifdef CONFIG_ARCH_BUTTONS
   /* Configure on-board BUTTONs if BUTTON support has been selected. */
- 
+
   board_button_initialize();
 #endif
 }
-Original file line number
+Diff line change
@@ Expand Up @@
                                struct SdDrCfg_s *cfg);
     UI_32 sdif_get_status(UI_32);
     #if defined(__cplusplus)
     }
     #endif
@@ Expand Down @@