LukJA · henryefranks · Sep 17, 2023 · Sep 17, 2023 · Sep 17, 2023 · Sep 17, 2023
diff --git a/.github/workflows/verif.yml b/.github/workflows/verif.yml
@@ -32,8 +32,11 @@ jobs:
     - name: Verify with cocotb & verilator
       working-directory: ./hdl/verif/cocotb
       run: |
-        source workflow_cfg.sh
-        pytest --junitxml=pytest_report.xml --report-log=logs/pytest.log -n auto
+        export COCOTB_TOP=$( realpath . )
+        export HDL_TOP=$( realpath $COCOTB_TOP/../.. )
+        export RTL_TOP=$( realpath $HDL_TOP/rtl )
+        pytest --junitxml=pytest_report.xml --report-log=logs/pytest.log \
+               -n auto -W ignore::UserWarning
 
     - name: Generate report
       if: always()

diff --git a/.vscode/settings.json b/.vscode/settings.json
@@ -3,7 +3,9 @@
     "python.testing.pytestArgs": [
         "hdl/verif/cocotb",
         "softmodels/tests",
-        "-n=auto"
+        "-n=auto",
+        "-W ignore::UserWarning",
+        "-s"
     ],
     "python.testing.unittestEnabled": false,
     "python.testing.pytestEnabled": true,

diff --git a/cocotb_env b/cocotb_env
@@ -1,11 +1,3 @@
 COCOTB_TOP="hdl/verif/cocotb"
 HDL_TOP="hdl"
 RTL_TOP="hdl/rtl"
-
-COCOTB_HDL_TIMEUNIT=1ns
-COCOTB_HDL_TIMEPRECISION=1ps
-
-TOPLEVEL_LANG=verilog
-
-SIM=verilator
-SIM_BUILD_ARGS="--trace --trace-fst --trace-structs --coverage"
diff --git a/hdl/rtl/alu/posit32_alu.sv b/hdl/rtl/alu/posit32_alu.sv
diff --git a/hdl/rtl/alu/posit64_alu.sv b/hdl/rtl/alu/posit64_alu.sv
diff --git a/hdl/rtl/decode/henry_decoder/posit32_decode.sv b/hdl/rtl/decode/henry_decoder/posit32_decode.sv
diff --git a/hdl/rtl/decode/henry_decoder/posit64_decode.sv b/hdl/rtl/decode/henry_decoder/posit64_decode.sv
diff --git a/hdl/rtl/decode/henry_decoder/posit_variable_count_regime.sv b/hdl/rtl/decode/henry_decoder/posit_variable_count_regime.sv
diff --git a/hdl/rtl/decode/henry_decoder/posit_variable_decode.sv b/hdl/rtl/decode/henry_decoder/posit_variable_decode.sv
diff --git a/hdl/rtl/typedef/common.sv → hdl/rtl/include/common.svh b/hdl/rtl/typedef/common.sv → hdl/rtl/include/common.svh
@@ -1,3 +1,8 @@
+`ifndef _COMMON_VH_
+`define _COMMON_VH_
+
 package common;
     typedef enum logic { POS, NEG } sign_t;
 endpackage
+
+`endif // _COMMON_VH_
diff --git a/hdl/rtl/typedef/posit_types.sv → hdl/rtl/include/posit_types.svh b/hdl/rtl/typedef/posit_types.sv → hdl/rtl/include/posit_types.svh
@@ -1,3 +1,6 @@
+`ifndef _POSIT_VH_
+`define _POSIT_VH_
+
 package posit_types;
 
     /* handy logic type for sign bit */
@@ -21,3 +24,5 @@ package posit_types;
     } posit64_t;
 
 endpackage
+
+`endif // _POSIT_VH_
diff --git a/hdl/rtl/alu/adder/mantissa_adder.sv → hdl/rtl/src/alu/adder/mantissa_adder.sv b/hdl/rtl/alu/adder/mantissa_adder.sv → hdl/rtl/src/alu/adder/mantissa_adder.sv
diff --git a/hdl/rtl/alu/adder/normalise.sv → hdl/rtl/src/alu/adder/normalise.sv b/hdl/rtl/alu/adder/normalise.sv → hdl/rtl/src/alu/adder/normalise.sv
diff --git a/hdl/rtl/alu/adder/posit_adder.sv → hdl/rtl/src/alu/adder/posit_adder.sv b/hdl/rtl/alu/adder/posit_adder.sv → hdl/rtl/src/alu/adder/posit_adder.sv
diff --git a/hdl/rtl/alu/alu_ctrl.sv → hdl/rtl/src/alu/alu_ctrl.sv b/hdl/rtl/alu/alu_ctrl.sv → hdl/rtl/src/alu/alu_ctrl.sv
@@ -4,4 +4,4 @@ package alu_ctrl;
         ADD,
         SUB
     } operations_t;
-endpackage
+endpackage
diff --git a/hdl/rtl/alu/comparator.sv → hdl/rtl/src/alu/comparator.sv b/hdl/rtl/alu/comparator.sv → hdl/rtl/src/alu/comparator.sv
@@ -1,3 +1,5 @@
+`include "common.svh"
+
 import common::*;
 
 module comparator #(
@@ -44,4 +46,3 @@ module comparator #(
 
 
 endmodule : comparator
-
diff --git a/hdl/rtl/alu/ops/posit32_add.sv → hdl/rtl/src/alu/ops/posit32_add.sv b/hdl/rtl/alu/ops/posit32_add.sv → hdl/rtl/src/alu/ops/posit32_add.sv
diff --git a/hdl/rtl/alu/ops/posit32_sub.sv → hdl/rtl/src/alu/ops/posit32_sub.sv b/hdl/rtl/alu/ops/posit32_sub.sv → hdl/rtl/src/alu/ops/posit32_sub.sv
diff --git a/hdl/rtl/alu/ops/posit64_add.sv → hdl/rtl/src/alu/ops/posit64_add.sv b/hdl/rtl/alu/ops/posit64_add.sv → hdl/rtl/src/alu/ops/posit64_add.sv
diff --git a/hdl/rtl/alu/ops/posit64_sub.sv → hdl/rtl/src/alu/ops/posit64_sub.sv b/hdl/rtl/alu/ops/posit64_sub.sv → hdl/rtl/src/alu/ops/posit64_sub.sv
diff --git a/hdl/rtl/alu/posit_32b_add.sv → hdl/rtl/src/alu/posit_32b_add.sv b/hdl/rtl/alu/posit_32b_add.sv → hdl/rtl/src/alu/posit_32b_add.sv
@@ -1,3 +1,5 @@
+`include "common.svh"
+
 import common::*;
 
 module posit_32b_add (

diff --git a/hdl/rtl/alu/posit_32b_sub.sv → hdl/rtl/src/alu/posit_32b_sub.sv b/hdl/rtl/alu/posit_32b_sub.sv → hdl/rtl/src/alu/posit_32b_sub.sv
@@ -1,3 +1,5 @@
+`include "common.svh"
+
 import common::*;
 
 module posit_32b_sub (

diff --git a/hdl/rtl/alu/posit_7b_add.sv → hdl/rtl/src/alu/posit_7b_add.sv b/hdl/rtl/alu/posit_7b_add.sv → hdl/rtl/src/alu/posit_7b_add.sv
@@ -1,3 +1,5 @@
+`include "common.svh"
+
 import common::*;
 
 module posit_7b_add (

diff --git a/hdl/rtl/alu/posit_7b_sub.sv → hdl/rtl/src/alu/posit_7b_sub.sv b/hdl/rtl/alu/posit_7b_sub.sv → hdl/rtl/src/alu/posit_7b_sub.sv
@@ -1,3 +1,5 @@
+`include "common.svh"
+
 import common::*;
 
 module posit_7b_sub (

diff --git a/hdl/rtl/alu/two_comp.sv → hdl/rtl/src/alu/two_comp.sv b/hdl/rtl/alu/two_comp.sv → hdl/rtl/src/alu/two_comp.sv
@@ -1,4 +1,6 @@
 // takes a logic bus and reports the twos complement of it
+`include "common.svh"
+
 import common::*;
 
 module two_comp #(

diff --git a/...ode/henry_decoder/posit32_count_regime.sv → ...ode/henry_decoder/posit32_count_regime.sv b/...ode/henry_decoder/posit32_count_regime.sv → ...ode/henry_decoder/posit32_count_regime.sv
@@ -1,3 +1,5 @@
+`include "posit_types.svh"
+
 import posit_types::*;
 
 module count_regime_16 (

diff --git a/hdl/rtl/decode/henry_decoder/util/mux.sv → hdl/rtl/src/decode/henry_decoder/util/mux.sv b/hdl/rtl/decode/henry_decoder/util/mux.sv → hdl/rtl/src/decode/henry_decoder/util/mux.sv
diff --git a/...e/henry_decoder/util/priority_encoders.sv → ...e/henry_decoder/util/priority_encoders.sv b/...e/henry_decoder/util/priority_encoders.sv → ...e/henry_decoder/util/priority_encoders.sv
diff --git a/...rtl/decode/luke_decoder/count_lead_one.sv → ...src/decode/luke_decoder/count_lead_one.sv b/...rtl/decode/luke_decoder/count_lead_one.sv → ...src/decode/luke_decoder/count_lead_one.sv
diff --git a/.../decode/luke_decoder/count_lead_one_24.sv → .../decode/luke_decoder/count_lead_one_24.sv b/.../decode/luke_decoder/count_lead_one_24.sv → .../decode/luke_decoder/count_lead_one_24.sv
diff --git a/...tl/decode/luke_decoder/count_lead_zero.sv → ...rc/decode/luke_decoder/count_lead_zero.sv b/...tl/decode/luke_decoder/count_lead_zero.sv → ...rc/decode/luke_decoder/count_lead_zero.sv
diff --git a/...rtl/decode/luke_decoder/count_tail_one.sv → ...src/decode/luke_decoder/count_tail_one.sv b/...rtl/decode/luke_decoder/count_tail_one.sv → ...src/decode/luke_decoder/count_tail_one.sv
diff --git a/...tl/decode/luke_decoder/count_tail_zero.sv → ...rc/decode/luke_decoder/count_tail_zero.sv b/...tl/decode/luke_decoder/count_tail_zero.sv → ...rc/decode/luke_decoder/count_tail_zero.sv
diff --git a/.../decode/luke_decoder/find_first_n_ones.sv → .../decode/luke_decoder/find_first_n_ones.sv b/.../decode/luke_decoder/find_first_n_ones.sv → .../decode/luke_decoder/find_first_n_ones.sv
@@ -1,4 +1,6 @@
 // returns the input with only the MSB 1 set
+`include "common.svh"
+
 import common::*;
 
 module find_first_n_ones #(

diff --git a/...rtl/decode/luke_decoder/find_first_one.sv → ...src/decode/luke_decoder/find_first_one.sv b/...rtl/decode/luke_decoder/find_first_one.sv → ...src/decode/luke_decoder/find_first_one.sv
@@ -1,4 +1,6 @@
 // returns the input with only the MSB 1 set
+`include "common.svh"
+
 import common::*;
 
 module find_first_one #(

diff --git a/...rtl/decode/luke_decoder/format_decoder.sv → ...src/decode/luke_decoder/format_decoder.sv b/...rtl/decode/luke_decoder/format_decoder.sv → ...src/decode/luke_decoder/format_decoder.sv
@@ -1,5 +1,7 @@
 // takes a posit bus and extracts the relevant
 // regions as digital signed byte values
+`include "common.svh"
+
 import common::*;
 
 // Comb

diff --git a/hdl/rtl/dff.sv → hdl/rtl/src/dff/dff.sv b/hdl/rtl/dff.sv → hdl/rtl/src/dff/dff.sv
@@ -19,4 +19,3 @@ end
 // end
 // `endif
 endmodule : dff
-
diff --git a/hdl/rtl/encode/format_encoder.sv → hdl/rtl/src/encode/format_encoder.sv b/hdl/rtl/encode/format_encoder.sv → hdl/rtl/src/encode/format_encoder.sv
@@ -1,3 +1,5 @@
+`include "common.svh"
+
 import common::*;
 
 module format_encoder #(

diff --git a/hdl/verif/cocotb/postrun_util/process_results.py b/hdl/verif/cocotb/postrun_util/process_results.py
@@ -1,12 +1,18 @@
 import xml.etree.ElementTree as ET
 
-tree = ET.parse('../pytest_report.xml')
+from pathlib import Path
+
+
+root_filepath = (Path(__file__).parent / '..').resolve()
+
+tree = ET.parse(root_filepath / 'pytest_report.xml')
 root = tree.getroot()
 
 print('# Test Results')
 
-## GENERATE SUMMARY
-###################
+######################
+## GENERATE SUMMARY ##
+######################
 
 modules = {}
 failures = {}
@@ -30,9 +36,9 @@
     split_idx = module_name.rindex('.')
     mod_path = module_name[:split_idx].replace('.', '/')    
     mod_name = module_name[split_idx+1:]
-    dir_name = test_name.replace('test_', '')
-    result_filename = (
-        f"../sim_build/{mod_path}/{dir_name}/{test_name}.results.xml"
+    result_filename = str(
+        root_filepath /
+        f"sim_build/{mod_name}/{test_name}/{test_name}.results.xml"
     )
 
     if mod_path not in modules:
@@ -72,8 +78,8 @@
 
         try:
             test_tree = ET.parse(test['filename'])
-        except:
-            print("<h5>Internal error displaying test results.</h5>")
+        except Exception as e:
+            print(f"<h5>Internal error displaying test results: {e}.</h5>")
             continue
 
         test_root = test_tree.getroot()
@@ -83,7 +89,9 @@
         errors = {}
         to_process = {}
 
-        with open(f"../logs/generated/{item}/{test['test_name']}.log") as logfile:
+        log_filepath = root_filepath / f"logs/generated/{item}/{test['test_name']}.log"
+
+        with open(log_filepath) as logfile:
             for i, line in enumerate(logfile):
                 if 'failed' in line:
                     test_name = line.split(' ')[-2]
Original file line number	Diff line number	Diff line change
Expand Up		@@ -19,4 +19,3 @@ end
		// end
		// `endif
		endmodule : dff