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Support llvm.frexp intrinsic translation #2252

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merged 8 commits into from
Jan 29, 2024
Merged

Support llvm.frexp intrinsic translation #2252

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b38f04d
Support frexp intrinsic translation
vmaksimo Dec 5, 2023
99d3789
fix clang-tidy
vmaksimo Dec 5, 2023
043ef19
Merge remote-tracking branch 'origin/main' into HEAD
vmaksimo Dec 18, 2023
861583e
Merge remote-tracking branch 'origin/main' into HEAD
vmaksimo Jan 10, 2024
bffed05
Add assert for int type
vmaksimo Jan 10, 2024
492feb7
Apply suggestion
vmaksimo Jan 18, 2024
c6b3427
Merge remote-tracking branch 'origin/main' into HEAD
vmaksimo Jan 18, 2024
8eedb5a
Fix CI failures
vmaksimo Jan 18, 2024
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58 changes: 57 additions & 1 deletion lib/SPIRV/SPIRVWriter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2123,8 +2123,25 @@ LLVMToSPIRVBase::transValueWithoutDecoration(Value *V, SPIRVBasicBlock *BB,
return mapValue(V, BM->addUnreachableInst(BB));

if (auto *RI = dyn_cast<ReturnInst>(V)) {
if (auto *RV = RI->getReturnValue())
if (auto *RV = RI->getReturnValue()) {
if (auto *II = dyn_cast<IntrinsicInst>(RV)) {
if (II->getIntrinsicID() == Intrinsic::frexp) {
// create composite type from the return value and second operand
auto *FrexpResult = transValue(RV, BB);
SPIRVValue *IntFromFrexpResult =
static_cast<SPIRVExtInst *>(FrexpResult)->getArgValues()[1];
IntFromFrexpResult = BM->addLoadInst(IntFromFrexpResult, {}, BB);

std::vector<SPIRVId> Operands = {FrexpResult->getId(),
IntFromFrexpResult->getId()};
auto *Compos = BM->addCompositeConstructInst(transType(RV->getType()),
Operands, BB);

return mapValue(V, BM->addReturnValueInst(Compos, BB));
}
}
return mapValue(V, BM->addReturnValueInst(transValue(RV, BB), BB));
}
return mapValue(V, BM->addReturnInst(BB));
}

Expand Down Expand Up @@ -2284,6 +2301,20 @@ LLVMToSPIRVBase::transValueWithoutDecoration(Value *V, SPIRVBasicBlock *BB,
}

if (auto *Ext = dyn_cast<ExtractValueInst>(V)) {
if (auto *II = dyn_cast<IntrinsicInst>(Ext->getAggregateOperand())) {
if (II->getIntrinsicID() == Intrinsic::frexp) {
unsigned Idx = Ext->getIndices()[0];
auto *Val = transValue(II, BB);
if (Idx == 0)
return mapValue(V, Val);

// Idx = 1
SPIRVValue *IntFromFrexpResult =
static_cast<SPIRVExtInst *>(Val)->getArgValues()[1];
IntFromFrexpResult = BM->addLoadInst(IntFromFrexpResult, {}, BB);
return mapValue(V, IntFromFrexpResult);
}
}
return mapValue(V, BM->addCompositeExtractInst(
transScavengedType(Ext),
transValue(Ext->getAggregateOperand(), BB),
Expand Down Expand Up @@ -3641,6 +3672,7 @@ bool LLVMToSPIRVBase::isKnownIntrinsic(Intrinsic::ID Id) {
case Intrinsic::fabs:
case Intrinsic::floor:
case Intrinsic::fma:
case Intrinsic::frexp:
case Intrinsic::log:
case Intrinsic::log10:
case Intrinsic::log2:
Expand Down Expand Up @@ -3751,6 +3783,8 @@ static SPIRVWord getBuiltinIdForIntrinsic(Intrinsic::ID IID) {
return OpenCLLIB::Floor;
case Intrinsic::fma:
return OpenCLLIB::Fma;
case Intrinsic::frexp:
return OpenCLLIB::Frexp;
case Intrinsic::log:
return OpenCLLIB::Log;
case Intrinsic::log10:
Expand Down Expand Up @@ -3926,6 +3960,28 @@ SPIRVValue *LLVMToSPIRVBase::transIntrinsicInst(IntrinsicInst *II,
return BM->addExtInst(STy, BM->getExtInstSetId(SPIRVEIS_OpenCL), ExtOp, Ops,
BB);
}
case Intrinsic::frexp: {
if (!checkTypeForSPIRVExtendedInstLowering(II, BM))
break;
SPIRVWord ExtOp = getBuiltinIdForIntrinsic(IID);

SPIRVType *FTy = transType(II->getType()->getStructElementType(0));
SPIRVTypePointer *ITy = static_cast<SPIRVTypePointer *>(transPointerType(
II->getType()->getStructElementType(1), SPIRAS_Private));

unsigned BitWidth = ITy->getElementType()->getBitWidth();
BM->getErrorLog().checkError(BitWidth == 32, SPIRVEC_InvalidBitWidth,
std::to_string(BitWidth));

SPIRVValue *IntVal =
BM->addVariable(ITy, false, spv::internal::LinkageTypeInternal, nullptr,
"", ITy->getStorageClass(), BB);

std::vector<SPIRVValue *> Ops{transValue(II->getArgOperand(0), BB), IntVal};

return BM->addExtInst(FTy, BM->getExtInstSetId(SPIRVEIS_OpenCL), ExtOp, Ops,
BB);
}
// Binary FP intrinsics
case Intrinsic::copysign:
case Intrinsic::pow:
Expand Down
147 changes: 147 additions & 0 deletions test/llvm-intrinsics/frexp.ll
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@@ -0,0 +1,147 @@
; RUN: llvm-as %s -o %t.bc
; RUN: llvm-spirv %t.bc -spirv-text
; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
; RUN: llvm-spirv %t.bc -o %t.spv
; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
; RUN: llvm-dis %t.rev.bc
; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM

target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
target triple = "spir64-unknown-unknown"

; CHECK-SPIRV: ExtInstImport [[#ExtInstSetId:]] "OpenCL.std"

; CHECK-SPIRV: TypeInt [[#TypeInt:]] 32
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Do we want to make this CHECK-SPIRV-DAG in case the order changes in the future?

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Not sure about that - I don't think that types would be shuffled.
I guess we should proceed as is and add DAG checks only if the ordering problem appears.

; CHECK-SPIRV: TypeFloat [[#TypeFloat:]] 32
; CHECK-SPIRV: TypeStruct [[#TypeStrFloatInt:]] [[#TypeFloat]] [[#TypeInt]]
; CHECK-SPIRV: TypePointer [[#TypeIntPtr:]] 7 [[#TypeInt]]

; CHECK-SPIRV: TypeFloat [[#TypeDouble:]] 64
; CHECK-SPIRV: TypeStruct [[#TypeStrDoubleInt:]] [[#TypeDouble]] [[#TypeInt]]

; CHECK-SPIRV: TypeVector [[#VecFloat2:]] [[#TypeFloat]] 2
; CHECK-SPIRV: TypeVector [[#VecInt2:]] [[#TypeInt]] 2
; CHECK-SPIRV: TypeStruct [[#TypeStrFloatIntVec2:]] [[#VecFloat2]] [[#VecInt2]]

; CHECK-SPIRV: TypeVector [[#VecFloat4:]] [[#TypeFloat]] 4
; CHECK-SPIRV: TypeVector [[#VecInt4:]] [[#TypeInt]] 4
; CHECK-SPIRV: TypeStruct [[#TypeStrFloatIntVec4:]] [[#VecFloat4]] [[#VecInt4]]

; CHECK-SPIRV: TypeVector [[#VecDouble2:]] [[#TypeDouble]] 2
; CHECK-SPIRV: TypeStruct [[#TypeStrDoubleIntVec2:]] [[#VecDouble2]] [[#VecInt2]]

; CHECK-SPIRV: Constant [[#TypeFloat]] [[#NegatedZeroConst:]] 2147483648
; CHECK-SPIRV: Undef [[#TypeDouble]] [[#UndefDouble:]]
; CHECK-SPIRV: ConstantNull [[#VecFloat2]] [[#NullVecFloat2:]]
; CHECK-SPIRV: Constant [[#TypeFloat]] [[#ZeroConstFloat:]] 0
; CHECK-SPIRV: ConstantComposite [[#VecFloat2]] [[#ZeroesCompositeFloat:]] [[#ZeroConstFloat]] [[#NegatedZeroConst]]

; CHECK-LLVM: %[[StrTypeFloatInt:[a-z0-9.]+]] = type { float, i32 }
; CHECK-LLVM: %[[StrTypeDoubleInt:[a-z0-9.]+]] = type { double, i32 }
; CHECK-LLVM: %[[StrTypeFloatIntVec2:[a-z0-9.]+]] = type { <2 x float>, <2 x i32> }
; CHECK-LLVM: %[[StrTypeFloatIntVec4:[a-z0-9.]+]] = type { <4 x float>, <4 x i32> }
; CHECK-LLVM: %[[StrTypeDoubleIntVec2:[a-z0-9.]+]] = type { <2 x double>, <2 x i32> }

declare { float, i32 } @llvm.frexp.f32.i32(float)
declare { double, i32 } @llvm.frexp.f64.i32(double)
declare { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float>)
declare { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float>)
declare { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double>)

; CHECK-SPIRV: Function [[#TypeStrFloatInt:]]
; CHECK-SPIRV: Variable [[#TypeIntPtr]] [[#IntVar:]] 7
; CHECK-SPIRV: ExtInst [[#TypeFloat]] [[#FrexpId:]] [[#ExtInstSetId]] frexp [[#NegatedZeroConst]] [[#IntVar]]
; CHECK-SPIRV: Load [[#]] [[#LoadId:]] [[#]]
; CHECK-SPIRV: CompositeConstruct [[#TypeStrFloatInt]] [[#ComposConstr:]] [[#FrexpId]] [[#LoadId]]
; CHECK-SPIRV: ReturnValue [[#ComposConstr]]

; CHECK-LLVM: %[[#IntVar:]] = alloca i32
; CHECK-LLVM: %[[Frexp:[a-z0-9]+]] = call spir_func float @_Z5frexpfPi(float -0.000000e+00, ptr %[[#IntVar]])
; CHECK-LLVM: %[[#LoadIntVar:]] = load i32, ptr %[[#IntVar]]
; CHECK-LLVM: %[[#AllocaStrFloatInt:]] = alloca %[[StrTypeFloatInt]]
; CHECK-LLVM: %[[GEPFloat:[a-z0-9]+]] = getelementptr inbounds %structtype, ptr %[[#AllocaStrFloatInt]], i32 0, i32 0
; CHECK-LLVM: store float %[[Frexp]], ptr %[[GEPFloat]]
; CHECK-LLVM: %[[GEPInt:[a-z0-9]+]] = getelementptr inbounds %structtype, ptr %[[#AllocaStrFloatInt]], i32 0, i32 1
; CHECK-LLVM: store i32 %[[#LoadIntVar]], ptr %[[GEPInt]]
; CHECK-LLVM: %[[LoadStrFloatInt:[a-z0-9]+]] = load %[[StrTypeFloatInt]], ptr %[[#AllocaStrFloatInt]]
; CHECK-LLVM: ret %[[StrTypeFloatInt]] %[[LoadStrFloatInt]]
define { float, i32 } @frexp_negzero() {
%ret = call { float, i32 } @llvm.frexp.f32.i32(float -0.0)
ret { float, i32 } %ret
}

; CHECK-SPIRV: ExtInst [[#TypeDouble]] [[#]] [[#ExtInstSetId]] frexp [[#UndefDouble]] [[#]]
; CHECK-LLVM: call spir_func double @_Z5frexpdPi(double undef, ptr %[[#]])
; CHECK-LLVM: ret %[[StrTypeDoubleInt]]
define { double, i32 } @frexp_undef() {
%ret = call { double, i32 } @llvm.frexp.f64.i32(double undef)
ret { double, i32 } %ret
}

; CHECK-SPIRV: ExtInst [[#VecFloat2]] [[#]] [[#ExtInstSetId]] frexp [[#NullVecFloat2]] [[#]]
; CHECK-LLVM: call spir_func <2 x float> @_Z5frexpDv2_fPDv2_i(<2 x float> zeroinitializer, ptr %[[#]])
; CHECK-LLVM: ret %[[StrTypeFloatIntVec2]]
define { <2 x float>, <2 x i32> } @frexp_zero_vector() {
%ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> zeroinitializer)
ret { <2 x float>, <2 x i32> } %ret
}

; CHECK-SPIRV: ExtInst [[#VecFloat2]] [[#]] [[#ExtInstSetId]] frexp [[#ZeroesCompositeFloat]] [[#]]
; CHECK-LLVM: call spir_func <2 x float> @_Z5frexpDv2_fPDv2_i(<2 x float> <float 0.000000e+00, float -0.000000e+00>, ptr %[[#]])
; CHECK-LLVM: ret %[[StrTypeFloatIntVec2]]
define { <2 x float>, <2 x i32> } @frexp_zero_negzero_vector() {
%ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> <float 0.0, float -0.0>)
ret { <2 x float>, <2 x i32> } %ret
}

; CHECK-SPIRV: ExtInst [[#VecFloat4]] [[#]] [[#ExtInstSetId]] frexp [[#]] [[#]]
; CHECK-LLVM: call spir_func <4 x float> @_Z5frexpDv4_fPDv4_i(<4 x float> <float 1.600000e+01, float -3.200000e+01, float undef, float 9.999000e+03>, ptr %[[#]])
; CHECK-LLVM: ret %[[StrTypeFloatIntVec4]]
define { <4 x float>, <4 x i32> } @frexp_nonsplat_vector() {
%ret = call { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float> <float 16.0, float -32.0, float undef, float 9999.0>)
ret { <4 x float>, <4 x i32> } %ret
}

; CHECK-SPIRV: ExtInst [[#TypeFloat]] [[#]] [[#ExtInstSetId]] frexp [[#]] [[#]]
; CHECK-SPIRV: ExtInst [[#TypeFloat]] [[#]] [[#ExtInstSetId]] frexp [[#]] [[#]]
; CHECK-LLVM: %[[#IntVar1:]] = alloca i32
; CHECK-LLVM: %[[Frexp0:[a-z0-9.]+]] = call spir_func float @_Z5frexpfPi(float %x, ptr %[[#IntVar1]])
; CHECK-LLVM: %[[#IntVar2:]] = alloca i32
; CHECK-LLVM: %[[Frexp1:[a-z0-9.]+]] = call spir_func float @_Z5frexpfPi(float %[[Frexp0]], ptr %[[#IntVar2]])
; CHECK-LLVM: %[[#LoadIntVar:]] = load i32, ptr %[[#IntVar2]]
; CHECK-LLVM: %[[#AllocaStrFloatInt:]] = alloca %[[StrTypeFloatInt]]
; CHECK-LLVM: %[[GEPFloat:[a-z0-9]+]] = getelementptr inbounds %structtype, ptr %[[#AllocaStrFloatInt]], i32 0, i32 0
; CHECK-LLVM: store float %[[Frexp1]], ptr %[[GEPFloat]]
; CHECK-LLVM: %[[GEPInt:[a-z0-9]+]] = getelementptr inbounds %structtype, ptr %[[#AllocaStrFloatInt]], i32 0, i32 1
; CHECK-LLVM: store i32 %[[#LoadIntVar]], ptr %[[GEPInt]]
; CHECK-LLVM: %[[LoadStrFloatInt:[a-z0-9]+]] = load %[[StrTypeFloatInt]], ptr %[[#AllocaStrFloatInt]]
; CHECK-LLVM: ret %[[StrTypeFloatInt]] %[[LoadStrFloatInt]]
define { float, i32 } @frexp_frexp(float %x) {
%frexp0 = call { float, i32 } @llvm.frexp.f32.i32(float %x)
%frexp0.0 = extractvalue { float, i32 } %frexp0, 0
%frexp1 = call { float, i32 } @llvm.frexp.f32.i32(float %frexp0.0)
ret { float, i32 } %frexp1
}

; CHECK-SPIRV: ExtInst [[#VecDouble2]] [[#]] [[#ExtInstSetId]] frexp [[#]] [[#]]
; CHECK-SPIRV: ExtInst [[#VecDouble2]] [[#]] [[#ExtInstSetId]] frexp [[#]] [[#]]
; CHECK-LLVM: %[[Frexp0:[a-z0-9.]+]] = call spir_func <2 x double> @_Z5frexpDv2_dPDv2_i(<2 x double> %x, ptr %[[#]])
; CHECK-LLVM: call spir_func <2 x double> @_Z5frexpDv2_dPDv2_i(<2 x double> %[[Frexp0]], ptr %[[#]])
; CHECK-LLVM: ret %[[StrTypeDoubleIntVec2]]
define { <2 x double>, <2 x i32> } @frexp_frexp_vector(<2 x double> %x) {
%frexp0 = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %x)
%frexp0.0 = extractvalue { <2 x double>, <2 x i32> } %frexp0, 0
%frexp1 = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %frexp0.0)
ret { <2 x double>, <2 x i32> } %frexp1
}

; CHECK-SPIRV: ExtInst [[#TypeFloat]] [[#]] [[#ExtInstSetId]] frexp [[#]] [[#]]
; CHECK-LLVM: %[[#IntVar:]] = alloca i32
; CHECK-LLVM: %[[Frexp:[a-z0-9.]+]] = call spir_func float @_Z5frexpfPi(float %x, ptr %[[#IntVar]])
; CHECK-LLVM: %[[LoadVar:[a-z0-9.]+]] = load i32, ptr %[[#IntVar]]
; CHECK-LLVM: ret i32 %[[LoadVar]]
define i32 @frexp_frexp_get_int(float %x) {
%frexp0 = call { float, i32 } @llvm.frexp.f32.i32(float %x)
%frexp0.0 = extractvalue { float, i32 } %frexp0, 1
ret i32 %frexp0.0
}
14 changes: 14 additions & 0 deletions test/negative/frexp_unsupported_signature.ll
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@@ -0,0 +1,14 @@
; RUN: llvm-as %s -o %t.bc
; RUN: not llvm-spirv %t.bc 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR

; CHECK-ERROR: InvalidBitWidth: Invalid bit width in input: 16

target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
target triple = "spir64-unknown-unknown"

declare { <2 x float>, <2 x i16> } @llvm.frexp.v2f32.v2i16(<2 x float>)

define { <2 x float>, <2 x i16> } @frexp_zero_vector() {
%ret = call { <2 x float>, <2 x i16> } @llvm.frexp.v2f32.v2i16(<2 x float> zeroinitializer)
ret { <2 x float>, <2 x i16> } %ret
}
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