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Add translation of fast math flags for binary arithmetic ops
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This replaces SPIR-V assembly tests for translation of FPFastMathMode
decorations with transcoding tests, adding a single SPIR-V assembly test
for the translation of the combination of the Fast and NotNaN flags.
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StuartDBrady authored and svenvh committed Mar 31, 2020
1 parent cb3be86 commit 4a4e0ae
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Showing 14 changed files with 398 additions and 275 deletions.
24 changes: 24 additions & 0 deletions lib/SPIRV/SPIRVWriter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1348,6 +1348,30 @@ bool LLVMToSPIRV::transDecoration(Value *V, SPIRVValue *BV) {
}
}

if (auto BVF = dyn_cast_or_null<FPMathOperator>(V)) {
auto Opcode = BVF->getOpcode();
if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub ||
Opcode == Instruction::FMul || Opcode == Instruction::FDiv ||
Opcode == Instruction::FRem) {
FastMathFlags FMF = BVF->getFastMathFlags();
SPIRVWord M{0};
if (FMF.isFast())
M |= FPFastMathModeFastMask;
else {
if (FMF.noNaNs())
M |= FPFastMathModeNotNaNMask;
if (FMF.noInfs())
M |= FPFastMathModeNotInfMask;
if (FMF.noSignedZeros())
M |= FPFastMathModeNSZMask;
if (FMF.allowReciprocal())
M |= FPFastMathModeAllowRecipMask;
}
if (M != 0)
BV->setFPFastMathMode(M);
}
}

return true;
}

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10 changes: 10 additions & 0 deletions lib/SPIRV/libSPIRV/SPIRVValue.cpp
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Expand Up @@ -111,4 +111,14 @@ void SPIRVValue::setNoUnsignedWrap(bool HasNoUnsignedWrap) {
}
}

void SPIRVValue::setFPFastMathMode(SPIRVWord M) {
if (M == 0) {
eraseDecorate(DecorationFPFastMathMode);
return;
}
addDecorate(new SPIRVDecorate(DecorationFPFastMathMode, this, M));
SPIRVDBG(spvdbgs() << "Set fast math mode to " << M << " for obj " << Id
<< "\n")
}

} // namespace SPIRV
1 change: 1 addition & 0 deletions lib/SPIRV/libSPIRV/SPIRVValue.h
Original file line number Diff line number Diff line change
Expand Up @@ -98,6 +98,7 @@ class SPIRVValue : public SPIRVEntry {
void setVolatile(bool IsVolatile);
void setNoSignedWrap(bool HasNoSignedWrap);
void setNoUnsignedWrap(bool HasNoUnsignedWrap);
void setFPFastMathMode(SPIRVWord FPFastMathMode);

void validate() const override {
SPIRVEntry::validate();
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38 changes: 38 additions & 0 deletions test/FPFastMathModeNotNaNFast.spvasm
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@@ -0,0 +1,38 @@
; REQUIRES: spirv-as
; RUN: spirv-as --target-env spv1.0 -o %t.spv %s
; RUN: spirv-val %t.spv
; RUN: llvm-spirv -r -o - %t.spv | llvm-dis | FileCheck %s
OpCapability Addresses
OpCapability Kernel
OpMemoryModel Physical32 OpenCL
OpEntryPoint Kernel %1 "testFPFastMathModeNotNaNFast"
OpName %a "a"
OpName %b "b"
OpName %r1 "r1"
OpName %r2 "r2"
OpName %r3 "r3"
OpName %r4 "r4"
OpName %r5 "r5"
OpDecorate %dec FPFastMathMode NotNaN|Fast
%dec = OpDecorationGroup
OpGroupDecorate %dec %r1 %r2 %r3 %r4 %r5
%void = OpTypeVoid
%float = OpTypeFloat 32
%5 = OpTypeFunction %void %float %float
%1 = OpFunction %void None %5
%a = OpFunctionParameter %float
%b = OpFunctionParameter %float
%6 = OpLabel
%r1 = OpFAdd %float %a %b
%r2 = OpFSub %float %a %b
%r3 = OpFMul %float %a %b
%r4 = OpFDiv %float %a %b
%r5 = OpFRem %float %a %b
OpReturn
OpFunctionEnd

; CHECK: %r1 = fadd fast float %a, %b
; CHECK: %r2 = fsub fast float %a, %b
; CHECK: %r3 = fmul fast float %a, %b
; CHECK: %r4 = fdiv fast float %a, %b
; CHECK: %r5 = frem fast float %a, %b
55 changes: 0 additions & 55 deletions test/OpFAdd.spvasm

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55 changes: 0 additions & 55 deletions test/OpFDiv.spvasm

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55 changes: 0 additions & 55 deletions test/OpFMul.spvasm

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55 changes: 0 additions & 55 deletions test/OpFRem.spvasm

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55 changes: 0 additions & 55 deletions test/OpFSub.spvasm

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