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PowerPC64 fixes #16404

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merged 6 commits into from
May 17, 2016
Merged

PowerPC64 fixes #16404

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7c1636e
Remove old PowerPC64 workaround for TOC issues
antonblanchard Apr 19, 2016
9b6e83f
Remove PowerPC little endian disassembly workaround
antonblanchard May 10, 2016
0892089
Disable fast isel on PowerPC64
antonblanchard May 11, 2016
5145551
Add LLVM patch that fixes PowerPC64 JIT issue
antonblanchard Apr 19, 2016
1b3f49e
Add LLVM patch that fixes some PowerPC64 little endian issues
antonblanchard May 10, 2016
d925dcd
Add LLVM patch that fixes verifier issue on PowerPC64
antonblanchard May 11, 2016
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2 changes: 1 addition & 1 deletion src/codegen.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5797,7 +5797,7 @@ extern "C" void jl_init_codegen(void)
targetFeatures);
assert(jl_TargetMachine && "Failed to select target machine -"
" Is the LLVM backend for this CPU enabled?");
#if defined(USE_MCJIT) && !defined(_CPU_ARM_)
#if defined(USE_MCJIT) && (!defined(_CPU_ARM_) && !defined(_CPU_PPC64_))
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I'm wonder what's wrong about fastisel... it works on AArch64 but not AArch32 for example......

What's the issue you see with FastISel?

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@antonblanchard antonblanchard May 17, 2016 •
edited by yuyichao
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Most likely a bug in the PowerPC64 fast-isel code, it doesn't get a whole lot of testing. We are working to find the bugs in llvm and fix them. One failure:

y = Float32(1)
i = trunc(Int32, y)

We get junk, instead of 1.

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So it's a different kind of failure with ARM backend, where the codegen messes up addressing mode and causes segfault...

// FastISel seems to be buggy for ARM. Ref #13321
if (jl_options.opt_level < 3)
jl_TargetMachine->setFastISel(true);
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