Update structure sizes according to cacheline size

Jbalkind · Nov 1, 2023 · 3549bfb · 3549bfb
1 parent df2d91b
commit 3549bfb
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Showing 4 changed files with 26 additions and 56 deletions.
diff --git a/.../chip/tile/l15/rtl/rf_l15_lrsc_flag.v.pyv → ...sign/chip/tile/l15/rtl/rf_l15_lrsc_flag.v b/.../chip/tile/l15/rtl/rf_l15_lrsc_flag.v.pyv → ...sign/chip/tile/l15/rtl/rf_l15_lrsc_flag.v
@@ -46,14 +46,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 `include "l15.tmp.h"
 
-<%
-  import pyhplib
-  from pyhplib import * 
-%>
 module rf_l15_lrsc_flag #(
    parameter L15_L1D_LINE_SIZE = 64, 
    localparam L15_NUM_ENTRIES = `CONFIG_L15_SIZE/L15_L1D_LINE_SIZE,
-   localparam L15_CACHE_INDEX_WIDTH = $clog2(L15_NUM_ENTRIES) - 2
+   localparam L15_CACHE_INDEX_WIDTH = $clog2(L15_NUM_ENTRIES) - 2,
+   localparam L15_SET_COUNT = L15_NUM_ENTRIES / `CONFIG_L15_ASSOCIATIVITY
 ) (
    input wire clk,
    input wire rst_n,
@@ -69,22 +66,14 @@ module rf_l15_lrsc_flag #(
    output wire [3:0] read_data
    );
 
-<%
-   linesize = 16
-   numset = int(int(CONFIG_L15_SIZE)/int(CONFIG_L15_ASSOCIATIVITY)/linesize)
-%>
-
-localparam L15_CACHE_INDEX_VECTOR_WIDTH = L15_NUM_ENTRIES/4;
-
-
 // reg read_valid_f;
 reg [L15_CACHE_INDEX_WIDTH-1:0] read_index_f;
 reg [L15_CACHE_INDEX_WIDTH-1:0] write_index_f;
 reg [3:0] write_data_f;
 reg [3:0] write_mask_f;
 reg write_valid_f;
 
-reg [3:0] regfile [0:L15_CACHE_INDEX_VECTOR_WIDTH-1];
+reg [3:0] regfile [0:L15_SET_COUNT-1];
 
 always @ (posedge clk)
 begin
@@ -113,16 +102,14 @@ begin
       write_mask_f <= write_mask;
    end
 end
-
+integer numset;
 always @ (posedge clk)
 begin
    if (!rst_n)
    begin
-      <%
-         for i in range (numset):
-            print("regfile[%d] <= 4'b0;" % (i))
-      %>
-      // regfile <= 1024'b0;
+      for (numset=0;numset<L15_SET_COUNT; numset = numset + 1) begin
+         regfile[numset] <= 4'b0;
+      end
    end
    else
    if (write_valid_f)

diff --git a/...n/chip/tile/l15/rtl/rf_l15_lruarray.v.pyv → ...esign/chip/tile/l15/rtl/rf_l15_lruarray.v b/...n/chip/tile/l15/rtl/rf_l15_lruarray.v.pyv → ...esign/chip/tile/l15/rtl/rf_l15_lruarray.v
@@ -42,17 +42,15 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 //rf_l15_lruarray.v
 
 `include "l15.tmp.h"
-<%
-  import pyhplib
-  from pyhplib import * 
-%>
+
 //`timescale 1 ns / 10 ps
 //`default_nettype none
 
 module rf_l15_lruarray #(
    parameter L15_L1D_LINE_SIZE = 64, 
    localparam L15_NUM_ENTRIES = `CONFIG_L15_SIZE/L15_L1D_LINE_SIZE,
-   localparam L15_CACHE_INDEX_WIDTH = $clog2(L15_NUM_ENTRIES) - 2
+   localparam L15_CACHE_INDEX_WIDTH = $clog2(L15_NUM_ENTRIES) - 2,
+   localparam L15_SET_COUNT = L15_NUM_ENTRIES / `CONFIG_L15_ASSOCIATIVITY
 
 ) (
    input wire clk,
@@ -69,18 +67,10 @@ module rf_l15_lruarray #(
    output wire [5:0] read_data
    );
 
-<%
-   linesize = 16
-   numset = int(int(CONFIG_L15_SIZE)/int(CONFIG_L15_ASSOCIATIVITY)/linesize)
-%>
-
-localparam L15_CACHE_INDEX_VECTOR_WIDTH = L15_NUM_ENTRIES/4;
-
-
 // reg read_valid_f;
 reg [L15_CACHE_INDEX_WIDTH-1:0] read_index_f;
 
-reg [5:0] regfile [0:L15_CACHE_INDEX_VECTOR_WIDTH-1];
+reg [5:0] regfile [0:L15_SET_COUNT-1];
 
 always @ (posedge clk)
 begin
@@ -99,15 +89,14 @@ end
 assign read_data = regfile[read_index_f];
 
 // Write port
+integer numset;
 always @ (posedge clk)
 begin
    if (!rst_n)
    begin
-      <%
-         for i in range (numset):
-            print("regfile[%d] <= 6'b0;" % (i))
-      %>
-      // regfile <= 1024'b0;
+      for (numset=0;numset<L15_SET_COUNT; numset = numset + 1) begin
+         regfile[numset] <= 6'b0;
+      end
    end
    else
    if (write_valid)

diff --git a/...esign/chip/tile/l15/rtl/rf_l15_mesi.v.pyv → piton/design/chip/tile/l15/rtl/rf_l15_mesi.v b/...esign/chip/tile/l15/rtl/rf_l15_mesi.v.pyv → piton/design/chip/tile/l15/rtl/rf_l15_mesi.v
@@ -48,14 +48,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 `include "l15.tmp.h"
 
-<%
-  import pyhplib
-  from pyhplib import * 
-%>
+
 module rf_l15_mesi #(
    parameter L15_L1D_LINE_SIZE = 64, 
    localparam L15_NUM_ENTRIES = `CONFIG_L15_SIZE/L15_L1D_LINE_SIZE,
-   localparam L15_CACHE_INDEX_WIDTH = $clog2(L15_NUM_ENTRIES) - 2
+   localparam L15_CACHE_INDEX_WIDTH = $clog2(L15_NUM_ENTRIES) - 2,
+   localparam L15_SET_COUNT = L15_NUM_ENTRIES / `CONFIG_L15_ASSOCIATIVITY
 
 )(
    input wire clk,
@@ -72,12 +70,9 @@ module rf_l15_mesi #(
    output wire [7:0] read_data
    );
 
-<%
-   linesize = 16
-   numset = int(int(CONFIG_L15_SIZE)/int(CONFIG_L15_ASSOCIATIVITY)/linesize)
-%>
 
-localparam L15_CACHE_INDEX_VECTOR_WIDTH = L15_NUM_ENTRIES/4;
+
+
 
 // reg read_valid_f;
 reg [L15_CACHE_INDEX_WIDTH-1:0] read_index_f;
@@ -86,7 +81,7 @@ reg [7:0] write_data_f;
 reg [7:0] write_mask_f;
 reg write_valid_f;
 
-reg [7:0] regfile [0:L15_CACHE_INDEX_VECTOR_WIDTH-1];
+reg [7:0] regfile [0:L15_SET_COUNT-1];
 
 always @ (posedge clk)
 begin
@@ -116,15 +111,14 @@ begin
    end
 end
 
+integer numset;
 always @ (posedge clk)
 begin
    if (!rst_n)
    begin
-      <%
-         for i in range (numset):
-            print("regfile[%d] <= 8'b0;" % (i))
-      %>
-      // regfile <= 1024'b0;
+      for (numset=0;numset<L15_SET_COUNT; numset = numset + 1) begin
+            regfile[numset] <= 8'b0;
+      end
    end
    else
    if (write_valid_f)

diff --git a/piton/design/chip/tile/l15/rtl/sram_wrappers/sram_l15_tag.v b/piton/design/chip/tile/l15/rtl/sram_wrappers/sram_l15_tag.v
@@ -57,7 +57,7 @@ output reg [`SRAM_WRAPPER_BUS_WIDTH-1:0] BIST_DOUT,
 input wire [`BIST_ID_WIDTH-1:0] SRAMID
 );
 
-localparam L15_CACHE_INDEX_VECTOR_WIDTH = L15_NUM_ENTRIES/4;
+localparam L15_CACHE_INDEX_VECTOR_WIDTH = L15_NUM_ENTRIES/`CONFIG_L15_ASSOCIATIVITY;
 
 
 `ifdef SYNTHESIZABLE_BRAM