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feat(esp32c5): Add USB-serial/JTAG stub support
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- Enables USB-serial/JTAG stub
- Enables USE_MAX_CPU_FREQ
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Dzarda7 committed Jun 28, 2024
1 parent b199534 commit e170bcc
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8 changes: 4 additions & 4 deletions esptool/targets/stub_flasher/stub_flasher_32c5.json
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"entry": 1082131910,
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"data": "DACEQO4IgEA6CYBAkgmAQGAKgEDMCoBAegqAQLYHgEAcCoBAXAqAQKYJgEBmB4BA2gmAQGYHgEDICIBADAmAQDoJgECSCYBA2giAQCAIgEBQCIBA1giAQCQNgEA6CYBA5AuAQNgMgECyBoBAAg2AQLIGgECyBoBAsgaAQLIGgECyBoBAsgaAQLIGgECyBoBAgAuAQLIGgEAADIBA2AyAQA==",
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"data": "FACEQG4KgEC+CoBAFguAQOQLgEBQDIBA/guAQDoJgECgC4BA4AuAQCoLgEDqCIBAXguAQOoIgEBICoBAjgqAQL4KgEAWC4BAWgqAQJ4JgEDOCYBAVgqAQKgOgEC+CoBAaA2AQGAOgEAqCIBAiA6AQCoIgEAqCIBAKgiAQCoIgEAqCIBAKgiAQCoIgEAqCIBABA2AQCoIgECGDYBAYA6AQA==",
"data_start": 1082469296,
"bss_start": 1082392576
}
12 changes: 11 additions & 1 deletion flasher_stub/include/soc_support.h
Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,7 @@
#endif // ESP32S3

#ifdef ESP32C5
#define WITH_USB_JTAG_SERIAL 0 // not implemented yet
#define WITH_USB_JTAG_SERIAL 1
#define IS_RISCV 1
#endif // ESP32C5

Expand Down Expand Up @@ -347,6 +347,16 @@
#define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */
#endif // ESP32C6

#if ESP32C5
#define UART_USB_JTAG_SERIAL 3

#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000
#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xD0) /* USB-JTAG-Serial, INTMTX_CORE0_USB_INTR_MAP_REG */

#define CLIC_EXT_INTR_NUM_OFFSET 16 /* For CLIC first 16 interrupts are reserved as internal */
#define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */
#endif // ESP32C5

#ifdef ESP32H2
#define UART_USB_JTAG_SERIAL 3

Expand Down
2 changes: 1 addition & 1 deletion flasher_stub/stub_io.c
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ static void stub_configure_rx_uart(void)
#if WITH_USB_JTAG_SERIAL
if (stub_uses_usb_jtag_serial()) {
#if IS_RISCV
#if ESP32P4
#if ESP32P4 || ESP32C5
WRITE_REG(INTERRUPT_CORE0_USB_INTR_MAP_REG, ETS_USB_INUM + CLIC_EXT_INTR_NUM_OFFSET);
#else
WRITE_REG(INTERRUPT_CORE0_USB_INTR_MAP_REG, ETS_USB_INUM); // Route USB interrupt to CPU
Expand Down
Binary file modified test/images/ram_helloworld/helloworld-esp32c5.bin
Binary file not shown.
4 changes: 2 additions & 2 deletions test/images/ram_helloworld/source/ld/app_32c5.ld
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
MEMORY {
iram : org = 0x40800d44, len = 0x100
dram : org = 0x40800e44, len = 0x100
iram : org = 0x40810f5c, len = 0x100
dram : org = 0x4081105c, len = 0x100
}

ENTRY(ram_main)
Expand Down
9 changes: 8 additions & 1 deletion test/test_esptool.py
Original file line number Diff line number Diff line change
Expand Up @@ -184,7 +184,14 @@ def run_esptool_process(cmd):
preload
and arg_preload_port
and arg_chip
in ["esp32c3", "esp32s3", "esp32c6", "esp32h2", "esp32p4"] # With U-JS
in [
"esp32c3",
"esp32s3",
"esp32c6",
"esp32h2",
"esp32p4",
"esp32c5",
] # With U-JS
):
port_index = base_cmd.index("--port") + 1
base_cmd[port_index] = arg_preload_port # Set the port to the preload one
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