Merge branch 'espressif:master' into main

Jason2866 · Dec 4, 2024 · 477897f · 477897f
2 parents 6d65068 + d47004e
commit 477897f
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Showing 5 changed files with 11 additions and 4 deletions.
diff --git a/docs/en/espefuse/inc/summary_ESP32-S3.rst b/docs/en/espefuse/inc/summary_ESP32-S3.rst
@@ -57,7 +57,7 @@
     DIS_PAD_JTAG (BLOCK0)                              Set this bit to disable JTAG in the hard way. JTAG = False R/W (0b0)
                                                         is disabled permanently
     STRAP_JTAG_SEL (BLOCK0)                            Set this bit to enable selection between usb_to_jt = False R/W (0b0)
-                                                       ag and pad_to_jtag through strapping gpio10 when b
+                                                       ag and pad_to_jtag through strapping gpio3 when b
                                                        oth reg_dis_usb_jtag and reg_dis_pad_jtag are equa
                                                        l to 0
 

diff --git a/espefuse/efuse_defs/esp32s3.yaml b/espefuse/efuse_defs/esp32s3.yaml
@@ -47,7 +47,7 @@ EFUSES:
   SECURE_BOOT_AGGRESSIVE_REVOKE    : {show: y, blk : 0, word: 3, pos: 21, len  : 1, start: 117, type      : bool, wr_dis  : 16, rd_dis: null, alt                            : '', dict             : '', desc: Set this bit to enable revoking aggressive secure boot, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'}
   DIS_USB_JTAG                     : {show: y, blk : 0, word: 3, pos: 22, len  : 1, start: 118, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: Set this bit to disable function of usb switch to jtag in module of usb device, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[22]', bloc: 'B14[6]'}
   DIS_USB_SERIAL_JTAG              : {show: y, blk : 0, word: 3, pos: 23, len  : 1, start: 119, type      : bool, wr_dis   : 2, rd_dis: null, alt                : DIS_USB_DEVICE, dict             : '', desc: Set this bit to disable usb device, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[23]', bloc: 'B14[7]'}
-  STRAP_JTAG_SEL                   : {show: y, blk : 0, word: 3, pos: 24, len  : 1, start: 120, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[24]', bloc: 'B15[0]'}
+  STRAP_JTAG_SEL                   : {show: y, blk : 0, word: 3, pos: 24, len  : 1, start: 120, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio3 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[24]', bloc: 'B15[0]'}
   USB_PHY_SEL                      : {show: y, blk : 0, word: 3, pos: 25, len  : 1, start: 121, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict: '{0: "internal PHY is assigned to USB Device while external PHY is assigned to USB OTG", 1: "internal PHY is assigned to USB OTG while external PHY is assigned to USB Device"}', desc: This bit is used to switch internal PHY and external PHY for USB OTG and USB Device, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[25]', bloc: 'B15[1]'}
   POWER_GLITCH_DSENSE              : {show: n, blk : 0, word: 3, pos: 26, len  : 2, start: 122, type  : 'uint:2', wr_dis  : 17, rd_dis: null, alt                            : '', dict             : '', desc: Sample delay configuration of power glitch, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27:26]', bloc: 'B15[3:2]'}
   FLASH_TPUW                       : {show: y, blk : 0, word: 3, pos: 28, len  : 4, start: 124, type  : 'uint:4', wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value.  Otherwise; the waiting time is twice the configurable value, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31:28]', bloc: 'B15[7:4]'}

diff --git a/esptool/targets/esp32c5.py b/esptool/targets/esp32c5.py
@@ -54,8 +54,8 @@ class ESP32C5ROM(ESP32C6ROM):
 
     UARTDEV_BUF_NO = 0x4085F51C  # Variable in ROM .bss which indicates the port in use
 
-    # Magic value for ESP32C5
-    CHIP_DETECT_MAGIC_VALUE = [0x1101406F]
+    # Magic values for ESP32C5 ECO0 and ECO1, respectively
+    CHIP_DETECT_MAGIC_VALUE = [0x1101406F, 0x63E1406F]
 
     FLASH_FREQUENCY = {
         "80m": 0xF,

diff --git a/esptool/targets/esp32c6.py b/esptool/targets/esp32c6.py
@@ -6,6 +6,7 @@
 import struct
 
 from .esp32c3 import ESP32C3ROM
+from ..loader import ESPLoader
 from ..util import FatalError, NotImplementedInROMError
 
 
@@ -194,6 +195,11 @@ def check_spi_connection(self, spi_connection):
                 "consider using other pins for SPI flash connection."
             )
 
+    def hard_reset(self):
+        # Bug in the USB-Serial/JTAG controller can cause the port to disappear
+        # if the chip is reset with RTC WDT, do a classic reset
+        ESPLoader.hard_reset(self)
+
 
 class ESP32C6StubLoader(ESP32C6ROM):
     """Access class for ESP32C6 stub loader, runs on top of ROM.

diff --git a/esptool/targets/esp32h2.py b/esptool/targets/esp32h2.py
@@ -80,6 +80,7 @@ def get_crystal_freq(self):
         return 32
 
     def hard_reset(self):
+        # RTC WDT reset not available, do a classic reset
         ESPLoader.hard_reset(self)
 
     def check_spi_connection(self, spi_connection):