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Fix test
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Jason2866 authored Nov 30, 2023
1 parent b465651 commit 363a7fc
Showing 1 changed file with 12 additions and 18 deletions.
30 changes: 12 additions & 18 deletions test/test_esptool.py
Original file line number Diff line number Diff line change
Expand Up @@ -949,21 +949,6 @@ def test_explicit_set_size_freq_mode(self):
class TestLoadRAM(EsptoolTestCase):
# flashing an application not supporting USB-CDC will make
# /dev/ttyACM0 disappear and USB-CDC tests will not work anymore

def verify_output(self, expected_out: List[bytes]):
"""Verify that at least one element of expected_out is in serial output"""
# Setting rtscts to true enables hardware flow control.
# This removes unwanted RTS logic level changes for some machines
# (and, therefore, chip resets)
# when the port is opened by the following function.
# As a result, the app loaded to RAM has a chance to run and send
# "Hello world" data without unwanted chip reset.
with serial.serial_for_url(arg_port, arg_baud, rtscts=True) as p:
p.timeout = 5
output = p.read(100)
print(f"Output: {output}")
assert any(item in output for item in expected_out)

@pytest.mark.quick_test
def test_load_ram(self):
"""Verify load_ram command
Expand All @@ -972,9 +957,18 @@ def test_load_ram(self):
"Hello world!\n" to the serial port.
"""
self.run_esptool(f"load_ram images/ram_helloworld/helloworld-{arg_chip}.bin")
self.verify_output(
[b"Hello world!", b'\xce?\x13\x05\x04\xd0\x97A\x11"\xc4\x06\xc67\x04']
)
try:
p = serial.serial_for_url(arg_port, arg_baud)
p.timeout = 5
output = p.read(100)
print(f"Output: {output}")
assert (
b"Hello world!" in output # xtensa
or b'\xce?\x13\x05\x04\xd0\x97A\x11"\xc4\x06\xc67\x04' in output # C3
)
finally:
p.close()


class TestDeepSleepFlash(EsptoolTestCase):
@pytest.mark.skipif(arg_chip != "esp8266", reason="ESP8266 only")
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