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Fix input ordering isses in Verilog generation #1294

Merged
merged 12 commits into from
May 21, 2021
Merged

Fix input ordering isses in Verilog generation #1294

merged 12 commits into from
May 21, 2021

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atomb
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@atomb atomb commented May 14, 2021 •
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This adapts SAWScript to GaloisInc/what4#122 allowing SAW to control the order of inputs in generated Verilog modules.

Fixes GaloisInc/what4#121 and the associated buggy counterexamples in SAW.

Aaron Tomb added 9 commits May 17, 2021 16:28
Adapt to What4 Verilog interface changes
7d6edba
Fix w4_abc_verilog counterexamples
af6e5ef
Adapt write_verilog to use improved input ordering
6543d15 
This builds on the same changes to What4 used to fix counterexamples
for w4_abc_verilog.
Add the changes to What4 that this code depends on
41c2a49
Add test for ABC/Verilog counterexample ordering
ad5ad12
Bump what4 submodule
b522cfd
Remove unused language extension
34c5afc
Remove unused import
636cbf2
Better solution to ordering of Verilog CEXs
6afd00e 
Instead of ad-hoc reversing in various places, adapt readFiniteValues
to be parameterized by endianness. Typical Verilog ordering, including
in that generated by What4, is little endian.
@atomb atomb force-pushed the at-verilog-inputs branch from 4c204a9 to 6afd00e Compare May 17, 2021 23:50
@atomb atomb marked this pull request as ready for review May 18, 2021 15:25
@atomb atomb requested review from robdockins and brianhuffman May 18, 2021 15:25
robdockins
robdockins approved these changes May 18, 2021
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minor nitpicks, otherwise looks OK to me

saw-core-what4/src/Verifier/SAW/Simulator/What4.hs Outdated Show resolved Hide resolved
saw-core/src/Verifier/SAW/FiniteValue.hs Show resolved Hide resolved
@atomb atomb added the PR: ready to merge Magic flag for pull requests to ask Mergify to merge given an approval and a successful CI run label May 21, 2021
@mergify mergify bot merged commit 5535b03 into master May 21, 2021
@mergify mergify bot deleted the at-verilog-inputs branch May 21, 2021 21:03
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@robdockins robdockins robdockins approved these changes

@brianhuffman brianhuffman Awaiting requested review from brianhuffman

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Successfully merging this pull request may close these issues.

The order of inputs in generated Verilog is unpredictable
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@atomb @robdockins