x86: Fix semantics for pinsrw, add semantics for pinsr{b,d,q}

[chameco]

Fixes are as follows:

• Treat the offset as relative to the end of the destination bitvector instead of the beginning. (A FIXME comment mentioned that this might need to be changed, and some testing corroborated this.)
• Only use some instruction-specific number of low bits from the immediate operand. This was resulting in different behavior when the immediate was "too big", for example something like pinsrd xmm1, eax, 5 should result in an offset of 5 & 0b11 = 1.

[travitch]

Could we get a comment explaining what w and c are here?

Are the mask values just taken from the ISA manual?

[chameco]

I've added some Haddock comments to those parameters.

The ISA manual specifies to use the 1, 2, 3, or 4 least significant bits of the immediate (depending on the instruction / whether the destination is MMX or XMM for pinsrw). I can add comments explaining the masks in this light if you'd like. I could also use a binary literal which makes the masks more apparent, but this would require enabling the BinaryLiterals extension.

[travitch]

Thanks, that looks good to me.