Skip to content
This repository has been archived by the owner on Sep 21, 2024. It is now read-only.

Commit

Permalink
WIP: Preliminary Design Document
Browse files Browse the repository at this point in the history
  • Loading branch information
cbebe committed Feb 6, 2024
1 parent da37887 commit 1958ab3
Show file tree
Hide file tree
Showing 4 changed files with 22 additions and 4 deletions.
Binary file added docs/ECE492_RISCV_PP.pdf
Binary file not shown.
15 changes: 15 additions & 0 deletions docs/PDD/biblio.bib
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,21 @@ @misc{gitlab
month={Feb}
}

@misc{pp,
title={RISC-V FPGA-based CPU and Language},
url={https://raw.githubusercontent.com/Fysh-Fyve/main/master/docs/ECE492_RISCV_PP.pdf},
year={2023},
month={Dec}
}

@misc{ppr,
title={Proposal Response: RISC-V FPGA-based CPU and Language},
url={https://raw.githubusercontent.com/Fysh-Fyve/main/master/docs/ECE492_RISCV_PPR_V01.pdf},
author={Ancheta, Charles and Al-Shamali, Yahya and Prince, Kyle},
year={2024},
month={Jan}
}

@misc{pandoc,
title={Creating a PDF | Pandoc User's Guide},
url={https://pandoc.org/MANUAL.html#creating-a-pdf},
Expand Down
6 changes: 4 additions & 2 deletions docs/PDD/md/00-head.md
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,9 @@ author: Charles Ancheta, Yahya Al-Shamali, Kyle Prince
csl: ieee-with-url.csl
---

<!-- This most likely does not need to be modified aside from removing the -->
<!-- reference -->

\setcounter{secnumdepth}{0}
\addtocontents{toc}{\protect\setcounter{tocdepth}{0}}

Expand Down Expand Up @@ -33,7 +36,6 @@ csl: ieee-with-url.csl
\addtocontents{toc}{\protect\setcounter{tocdepth}{3}}

References [@gitlab] must [@pandoc] be [@crack] used or else they don't show up
in the bibliography.
in the bibliography [@ppr] [@pp].

\newpage

5 changes: 3 additions & 2 deletions docs/PDD/md/02-concept-of-operation.md
Original file line number Diff line number Diff line change
@@ -1,11 +1,12 @@
# Concept of Operation

The high-level operation of the RISC-V FPGA-based CPU and Language is
illustrated by the following user stories and use cases \tpl{2 or 3 pages should
be enough}.
illustrated by the following user stories and use cases.

## User Stories

As an Electrical and Computer Engineering Student, I want to

\tpl{Have at most 3 paragraphs per user story, preferably one}

## Use Cases
Expand Down

0 comments on commit 1958ab3

Please sign in to comment.